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95VLP857AGLFT

P1-P3P4-P6P7-P9P10-P12P13-P13
7
ICS95VLP857
0956B—08/03/04
GND
ICS95VLP857
V
DD
V
DD
/2
V
(CLKC)
V
(CLKC)
SCOPE
C=14pF
-V
DD/2
-V
DD/2
-V
DD/2
V
DD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V
(TT)
V
(TT)
C=14pF
NOTE: V
(TT)
=
GND
t
c(n)
t
c(n+1)
t
jit(cc)
=t
c(n)
±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS95VLP857
Figure 3. Cycle-to-Cycle Jitter
8
ICS95VLP857
0956B—08/03/04
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=
1
n=
N
t
()n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t
(SK_O)
Y
#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y
X
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output
Skew
1
f
O
t
=
t
-
(jit_per) C(n)
1
f
O
Figure 6. Period Jitter
9
ICS95VLP857
0956B—08/03/04
Clock Inputs
and Outputs
80%
20%
80%
20%
Rise t
sl
Fall t
sl
V
ID
,V
OD
Figure 8. Input and Output Slew Rates
Parameter Measurement
Information
t
(hper_n)
t
(hper_n+1)
1
f
o
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
t
=-
(jit_Hper)
t
(jit_Hper_n)
1
2xf
O
P1-P3P4-P6P7-P9P10-P12P13-P13

95VLP857AGLFT

Mfr. #:
Buy 95VLP857AGLFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution LOW POWER 2.5V PLL CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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