6
ICS95VLP857
0956B—08/03/04
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, where
the cycle (t
c
) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
Timing Requirements
T
A
= 0 - 85°C; Supply Voltage A
VDD
, V
DD
= 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency freq
op
2.5V+0.2V @ 25
o
C
45 233 MHz
Application Frequency
Range
freq
App
2.5V+0.2V @ 25
o
C
95 220 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
15 µs
Switching Characteristics (see note 3)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-to high level
propagation delay time
t
PLH
1
CLK_IN to any output 3.5 ns
High-to low level propagation
delay time
t
PLL
1
CLK_IN to any output 3.5 ns
Output enable time t
EN
PD# to any output 3 ns
Output disable time tdis PD# to any output 3 ns
Period jitter T
it
er
100MHz to 200MHz -30 30 ps
Half-period jitter t(jit_hper) 100MHz to 200MHz -75 75 ps
Input clock slew rate t
sl
i
14V/ns
Output clock slew rate t
sl
o
12V/ns
Cycle to Cycle Jitter
1
T
c
c
-T
c
c
100MHz to 200MHz -50 50 ps
Static Phase Offset
t
static
hase offset
4
-50 0 50 ps
Output to Output Skew T
skew
40 ps