SL28DB200AZI

100 MHz Differential Buffer for PCI Express and SATA
SL28DB200
..........................Document #: 38-07722 Rev *C Page 1 of 8
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
Two differential 0.7V clock output pairs
OE# input for enabling SRC outputs
Individual OE controls
Low CTC jitter (< 50 ps)
•Spread Aware
3.3V operation
Industrial Temperature Grade -40
o
C to +85
o
C
16-pin TSSOP package
Functional Description
The SL28DB200 is a differential buffer capable of distributing
the Serial Reference Clock (SRC) for PCI Express Gen2 and
SATA implementations. The buffer enables the application
system to control the distribution of the SRC.
Applications
Network/Media Attached Storage
Routers/IP Gateways
Multi-function Printers
Block Diagram
Pin Configuration
16 TSSOP
SL28DB200
......................... Document #: 38-07722 Rev *C Page 2 of 8
Notes: I=Input, O=Output, DIF=Differential signal, SE=Single Ended, PWR=Power input, GND=Ground
Pin Description
Pin Name Type Description
2,3 SRCIN, SRCIN# I,DIF 0.7V Differential inputs
5,6,13,12 SRC[1:2], SRC[1:2]# O,DIF 0.7V Differential Clock Outputs
7,11 OE[1:2]# I,SE 3.3V LVTTL input for enabling differential outputs
15 IREF I A precision resistor 475 ohmis attached to this pin to set the differential
output current
1 VDDA PWR 3.3V Power Supply
16 VSSA GND Ground
8,10,14 VDD PWR 3.3V power supply for outputs
4,9 VSS GND Ground for outputs
Table 1. Buffer Power-up State Machine
State Description
S0 3.3V Buffer power off
S1 After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay
S2 Buffer waits for a valid clock on the SRCIN input
S3 Once a valid input is detected, the buffer enters state 3 and enables outputs for normal operation
Figure 1. Buffer Power-up State Diagram
SL28DB200
......................... Document #: 38-07722 Rev *C Page 3 of 8
Output Enable Clarification
OE# functionality allows for enabling and disabling individual
outputs. OE1# and OE2# are Active LOW inputs. Disabling the
outputs may be implemented by deasserting the OE# input
pin. If the OE# pin is deasserted, the output of interest will be
tri-stated. (The assertion and deassertion of this signal is
absolutely asynchronous.)
OE Assertion
All differential outputs that were tri-stated will resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2–6 SRC clock
periods. In addition, SRC clocks will be driven high within 15
ns of OE# assertion to a voltage greater than 200 mV
Absolute Maximum Conditions
OE Deassertion
The impact of deasserting OE# is that each corresponding
output will transition from normal operation to tri-state in a
glitch-free manner. The maximum latency from the
deassertion to tri-stated outputs is between 2–6 DIF clock
periods.
DC Electrical Specifications
Table 2. OE Functionality
OE# SRC,SRC#
0 Enable
1 Tri-State
Parameter Description Condition Min. Max. Unit
VDD Core Supply Voltage –0.5 4.6 V
VDDA Analog Supply Voltage –0.5 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 V
DD
+ 0.5 VDC
T
S
Temperature, Storage Non-functional –65 +150 °C
T
A
Temperature, Operating Ambient
(Commercial Grade)
Functional 0 85 °C
T
A
Temperature, Operating Ambient
(Industrial Grade)
Functional -40 85 °C
T
J
Temperature, Junction Functional 150 °C
ESD
HBM
ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) 2000 V
UL-94 Flammability Rating UL (Class) V–0
MSL Moisture Sensitivity Level 1
Parameter Description Condition Min. Max. Unit
VDDA
,
VDD
3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
IL
3.3V Input Low Voltage V
SS
– 0.5 0.8 V
V
IH
3.3V Input High Voltage 2.0 V
DD
+ 0.5 V
I
IL
Input Low Leakage Current except internal pull-up resistors, 0 < V
IN
< V
DD
–5 A
I
IH
Input High Leakage Current except internal pull-down resistors, 0 < V
IN
< V
DD
5 A
C
IN
Input Pin Capacitance 1.5 5 pF
C
OUT
Output Pin Capacitance –- 6 pF
L
IN
Pin Inductance 7 nH
I
DD3.3V
Dynamic Supply Current At max. load, Full Active, at 100MHz 60 mA

SL28DB200AZI

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products PCIe family, 1 diff input, 2 diff outputs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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