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R2A20169NP#W5

P1-P3P4-P6P7-P9P10-P10
Datasheet
R2A20169NP/SA/SP
Page 4 of 9
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
« Analog Part »
( Vcc,VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL=0V, Ta= -30 to +85deg, unless otherwise noted )
Item Symbol Test conditions
Limits
Unit
Min Typ Max
Current dissipation I
refU
VrefU=5V, VrefL=0V, IAO=0µA,
Data condition: at maximum current
- 1.5 3.0 mA
D/A converter upper
reference voltage range *2
V
refU
Vcc ³ 4.5V 3.5 - Vcc
V
Vcc < 4.5V 0.7Vcc - Vcc
D/A converter lower
reference voltage range *2
V
refL
Vcc ³ 4.5V GND - Vcc-3.5
V
Vcc < 4.5V GND - 0.3Vcc
Buffer amplifier output
voltage range
V
AO
IAO = +/- 100 µA 0.1 - Vcc – 0.1 V
I
AO = +/- 500 µA 0.2 - Vcc – 0.2 V
Buffer amplifier output
drive range
I
AO
Upper side saturation voltage = 0.3V,
Lower side saturation voltage = 0.2V
-1.0 - 1.0 mA
Differential nonlinearity S
DL
V
refU = 4.79V,
V
refL = 0.95V,
Vcc = 5.5V (15mV/LSB),
Without load (I
AO =0µA)
-0.7 - 0.7 LSB
Nonlinearity S
L -1.0 - 1.0 LSB
Zero code error S
ZERO -2.0 - 2.0 LSB
Full scale error S
FULL -2.0 - 2.0 LSB
Output capacitive load Co - - 0.1 µF
Buffer amplifier output
impedance
Ro - 5.0 - ohm
*2 : The output does not necessary be the value with the reference voltage setting range.
The output value is determined by the buffer amplifier output voltage range (V
AO).
Datasheet
R2A20169NP/SA/SP
Page 5 of 9
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
Item Symbol
Test conditions
Limits
Unit
Min Typ Max
Clock frequency f
CLK
- 1.0 10 MHz
Clock low pulse width t
CKL
40 - - ns
Clock high pulse width t
CKH
40 - - ns
Clock rise time t
CR
- - 200 ns
Clock fall time t
CF
- - 200 ns
Data setup time t
DCH
4 - - ns
Data hold time t
CHD
30 - - ns
LD setup time t
CHL
40
- - ns
LD hold time t
LDC
40 - - ns
LD high pulse width t
LDH
40 - - ns
Data output delay time t
DO
C
L
< 100 pF -10 - 50 ns
D/A output settling time t
LDD
Ta=25deg, C
L
<100pF, V
AO
: 0.5¨4.5V,
The time until the output becomes the final
value of 1/2 LSB.
- - 150 µs
AC Characteristics
Timing Chart
CLK
tCR tCF tCKH
tCKL
tDCH tCHD
tCHL
tLDH tLDC
tLDD
DI
LD
D/A
output
tDo
Do
output
( Vcc, VrefU = +5V +/-10%, Vcc >VrefU, GND=VrefL = 0V, Ta = -30 to +85deg, unless otherwise noted )
(Note) Timing chart above is a schematic representation of the timing of each signal type.
CLK signal input is High or Low regardless, LD signal High input is enabled.
Datasheet
R2A20169NP/SA/SP
Page 6 of 9
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
Digital Data Format
Last
LSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0 D1 D2 D3 D4 D5 D6 D7 D/A Output
0 0 0 0 0 0 0 0 (V
refU
– V
refL
) / 256 x 1 + V
refL
1 0 0 0 0 0 0 0 (V
refU
– V
refL
) / 256 x 2 + V
refL
0 1 0 0 0 0 0 0 (V
refU
– V
refL
) / 256 x 3 + V
refL
1 1 0 0 0 0 0 0 (V
refU
– V
refL
) / 256 x 4 + V
refL
: : : : : : : : :
0 1 1 1 1 1 1 1 (V
refU
– V
refL
) / 256 x 255 + V
refL
1 1 1 1 1 1 1 1 V
refU
First
MSB
DAC data
Channel
select data
Channel select data
D8 D9 D10 D11 Chanel Selection
0 0 0 0 Don’t care
0 0 0 1 Ao1 select
0 0 1 0 Ao2 select
0 0 1 1 Ao3 select
0 1 0 0 Ao4 select
0 1 0 1 Ao5 select
0 1 1 0 Ao6 select
0 1 1 1 Ao7 select
1 0 0 0 Ao8 select
1 0 0 1 Ao9 select
1 0 1 0 Ao10 select
1 0 1 1 Ao11 select
1 1 0 0 Ao12 select
1 1 0 1 Don’t care
1 1 1 0 Don’t care
1 1 1 1 Don’t care
DAC data
P1-P3P4-P6P7-P9P10-P10

R2A20169NP#W5

Mfr. #:
Buy R2A20169NP#W5
Manufacturer:
Renesas Electronics
Description:
Digital to Analog Converters - DAC I2C Bus I/O Expander
Lifecycle:
New from this manufacturer.
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