IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol Parameter
70T633/1S10
Com'l
& Ind
(6)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Unit
Min. Max. Min. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
10
____
12
____
15 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
10
____
12
____
15 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
10
____
12
____
15 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
10
____
12
____
15 ns
t
APS
Arbitration Priority Se t-up Time
(2)
2.5
____
2.5
____
2.5
____
ns
t
BDD
BUSY Disable to Valid Data
(3) ____
10
____
12
____
15 ns
t
WH
Write Hold After BUSY
(5)
7
____
9
____
12
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
7
____
9
____
12
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
14
____
16
____
20 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
14
____
16
____
20 ns
5670 tbl 15
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1,2,3)
Symbol Parameter
70T633/1S10
Com'l
& Ind
70T6331S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min. Max. Min. Max. Min. Max.
SLEEP MODE TIMING (ZZx=V
IH
)
t
ZZS
Sleep Mode Set Time 10
____
12
____
15
____
t
ZZR
Sleep Mode Reset Time 10
____
12
____
15
____
t
ZZPD
Sleep Mode Power Down Time
(4)
10
____
12
____
15
____
t
ZZPU
Sleep Mode Power Up Time
(4)
____
0
____
0
____
0
5670 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
4. This parameter is guaranteed by device characterization, but is not production tested.
