IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE
0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(4)
Symbol Parameter
70T633/1S10
Com'l
& Ind
(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
___ _
15 ns
t
ACE
Chip Enable Access Time
(3)
____
10
____
12
___ _
15 ns
t
ABE
Byte Enable Access Time
(3)
____
5
____
6
___ _
7ns
t
AOE
Output Enable Access Time
____
5
____
6
___ _
7ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time Chip Enable and Semaphore
(1,2)
3
____
3
____
3
____
ns
t
LZOB
Output Low-Z Time Output Enable and Byte Enable
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
040608ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
8
____
8
___ _
12 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)
____
4
____
6
___ _
8ns
t
SAA
Semaphore Address Access Time 2 10 2 12 2 15 ns
t
SOE
Semaphore Output Enable Access Time
____
5
____
6
___ _
7ns
5670 tbl 12
Symbol Parameter
70T633/1S10
Com'l
& Ind
(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCL E
t
WC
Write Cycle Time 10
____
12
____
15
____
ns
t
EW
Chip Enable to End-of-Write
(3)
7
____
9
____
12
____
ns
t
AW
Address Valid to End-of-Write 7
____
9
____
12
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 7
____
9
____
12
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 5
____
7
____
10
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
4
____
6
____
8ns
t
OW
Output Active from End-of-Write
(1,2)
3
____
3
____
3
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
5670 tbl 13