5
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Names
Left Port Right Port Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables (Input)
R/W
L
R/W
R
Read/Write Enable (Input)
OE
L
OE
R
Output Enable (Input)
A
0L
- A
18L
(1)
A
0R
- A
18R
(1)
Address (Input)
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable (Input)
INT
L
INT
R
Interrupt Flag (Output)
BUSY
L
BUSY
R
Busy Flag (Output)
UB
L
UB
R
Upper Byte Select (Input)
LB
L
LB
R
Lower Byte Select (Input)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(2)
(Input)
OPT
L
OPT
R
Option for selecting V
DDQX
(2,3)
(Input)
ZZ
L
ZZ
R
Sleep Mode Pin
(4)
(Input)
M/S Master or Slave Select (Input)
(5)
V
DD
Power (2.5V)
(2)
(Input)
V
SS
Ground (0V) (Input)
TDI Test Data Input
TDO Test Data Output
TCK Test Logic Clock (10MHz) (Input)
TMS Test Mode Select (Input)
TRST
Reset (Initialize TAP Controller) (Input)
5670 tbl 01
NOTES:
1. Address A
18x is a NC for IDT70T631.
2. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/O
X.
3. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
5. BUSY is an input as a Slave (M/S=V
IL) and an output when it is a Master
(M/S=V
IH).