NCP1379
http://onsemi.com
18
SHORT−CIRCUIT OR OVERLOAD MODE
Figure 33 shows the implementation of the fault timer.
ZCD/OPP
Laux
S
R
Q
Q
CS
Rsense
LEB1
+
−
Soft−start
Vcc
au x
V
CC
management
latch
VDD
fau l t
grand
reset
grand
reset
DRV
Soft −s t art end ?
t hen 1
else 0
IpFlag
+
−
SS en d
PW Mr eset
Up
Down
TIMER
Reset
VCCstop
FB/4
OPP
V
IL IM IT
+
−
LEB2
V
CS(stop)
CsStop
CsStop
VCCstop
Figure 33. Fault Detection Schematic
When the current in the MOSFET is higher than V
ILIM
/R
sense
, “Max Ip” comparator trips and the digital timer
starts counting: the timer count is incremented each 10 ms.
When the current comes back within safe limits, “Max Ip”
comparator becomes silent and the timer count down: the
timer count is decremented each 10 ms. In normal overload
conditions the timer reaches its completion when it has
counted up 8 times 10 ms.
When the timers reaches its completion, the circuit enter
auto−recovery mode: the circuit stops all operations during
1.2 s typically and re−start. This ensures a low duty−cycle
burst operation in fault mode (around 6.7%).
In parallel to the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (t
BCS
) and a
threshold of 1.2 V is able to sense winding short−circuit and
immediately stop the controller. This additional protection
is also auto−recovery.
