MC100EL14DWR2G

© Semiconductor Components Industries, LLC, 2008
November, 2008 Rev. 8
1 Publication Order Number:
MC100EL14/D
MC100EL14
5V ECL 1:5 Clock
Distribution Chip
The MC100EL14 is a low skew 1:5 clock distribution chip designed
explicitly for low skew clock distribution applications. The V
BB
pin, an
internally generated voltage supply, is available to this device only.
For single-ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The EL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open and pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock
input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
Features
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 4.2 V to 5.7 V
Q Output will Default LOW with Inputs Open or at V
EE
Internal Input Pulldown Resistors on All Inputs, Pullup Resistors
on Inverted Inputs
SOIC20L
DW SUFFIX
CASE 751D
MARKING DIAGRAM
http://onsemi.com
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
20
1
100EL14
AWLYYWWG
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
MC100EL14
http://onsemi.com
2
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MC100EL14
http://onsemi.com
3
Figure 1. Logic Diagram and Pinout Assignment
Q1 Q2 Q3 Q4
1718 16 15 14 13 12
43 56789
V
CC
11
10
Q4Q3Q2Q1
NC SCLK CLK CLK V
BB
SEL V
EE
D
Q
1 0
Q0
1920
21
V
CC
Q0
EN
* All V
CC
pins are tied together on the die.
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
PIN FUNCTION
CLK, CLK ECL Diff Clock Inputs
SCLK ECL Scan Clock Input
EN ECL Sync Enable
SEL ECL Clock Select Input
Q
04,
Q
04
ECL Diff Clock Outputs
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
NC No Connect
Table 2. FUNCTION TABLE
CLK* SCLK* SEL* EN* Q
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L
(Note )
1. On next negative transition of CLK or SCLK
**Pins will default low when left open.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
75 kW
ESD Protection Human Body Model
Machine Model
Charge Device Model
> 2 kV
> 200 V
> 4 kV
Moisture Sensitivity (Note 2)
Pb
PbFree
Level 1
Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 303 Devices
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

MC100EL14DWR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 5V ECL 1:5 Clock Distribution
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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