M27C64A Summary description
7/22
Figure 2. DIP Connections
Figure 3. Pin Connections
Q2
V
SS
A3
A0
Q0
Q1
A2
A1
G
Q5
A10
E
Q3
A11
Q7
Q6
Q4
NC
PA12
A4
V
PP
V
CC
A7
AI00835
M27C64A
8
1
2
3
4
5
6
7
9
10
11
12
13
14
20
19
18
17
16
15
A6
A5
A9
A8
28
27
26
25
24
23
22
21
AI00836
NC
A8
A10
Q4
17
A0
NC
Q0
Q1
Q2
DU
Q3
A6
A3
A2
A1
A5
A4
9
P
A9
1
V
PP
A11
Q6
A7
Q7
32
DU
V
CC
M27C64A
A12
NC
Q5
G
E
25
V
SS
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Device operation M27C64A
8/22
2 Device operation
The modes of operation of the M27C64A are listed in the Operating Modes table. A single
power supply is required in the read mode. All inputs are TTL levels except for V
PP
and 12V
on A9 for Electronic Signature.
2.1 Read mode
The M27C64A has two control functions, both of which must be logically active in order to
obtain data at the outputs. Chip Enable (E
) is the power control and should be used for
device selection. Output Enable (G
) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that the addresses are stable,
the address access time (t
AVQV
) is equal to the delay from E to output (t
ELQV
). Data is
available at the output after a delay of t
GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for at least t
AVQV
-t
GLQV
.
2.2 Standby mode
The M27C64A has a standby mode which reduces the active current from 30mA to 100µA.
The M27C64A is placed in the standby mode by applying a CMOS high signal to the E
input.
When in the standby mode, the outputs are in a high impedance state, independent of the G
input.
2.3 Two Line output control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
The lowest possible memory power dissipation
Complete assurance that output bus contention will not occur
For the most efficient use of these two control lines, E
should be decoded and used as the
primary device selecting function, while G
should be made a common connection to all
devices in the array and connected to the READ
line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
2.4 System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the devices. The supply current, I
CC
, has three segments that are of interest to
the system designer: the standby current level, the active current level, and transient current
peaks that are produced by the falling and rising edges of E
. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can be suppressed by complying with the
two line output control and by properly selected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor be used on every device between V
CC
and V
SS
. This should
Obsolete Product(s) - Obsolete Product(s)
M27C64A Device operation
9/22
be a high frequency capacitor of low inherent inductance and should be placed as close to
the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the bulk capacitor is to overcome the voltage
drop caused by the inductive effects of PCB traces.
2.5 Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C64A are in the
"1" state. Data is introduced by selectively programming "0"s into the desired bit locations.
Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word.
The only way to change a "0" to a "1" is by die exposition to ultraviolet light (UV EPROM).
The M27C64A is in the programming mode when V
PP
input is at 12.5V, E is at V
IL
and P is
pulsed to V
IL
. The data to be programmed is applied to 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are TTL. V
CC
is specified to be 6V
± 0.25V.
2.6 High-speed programming
The high speed programming algorithm, described in Figure 4, rapidly programs the
M27C64A using an efficient and reliable method, particularly suited to the production
programming environment. An individual device will take around 1 minute to program.
Figure 4. Programming Flowchart
AI01167
n = 1
Last
Addr
VERIFY
P = 1ms Pulse
++n
> 25
++ Addr
V
CC
= 6V, V
PP
= 12.5V
FAIL
CHECK ALL BYTES
1st: V
CC
= 6V
2nd: V
CC
= 4.2V
YES
NO
YES
NO
YES
NO
P = 3ms Pulse by n
Obsolete Product(s) - Obsolete Product(s)

M27C64A-20F1

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EPROM 64K (8Kx8) 200ns
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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