NCP112
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8
PIN FUNCTION DESCRIPTION
Main Line Sensing − VS33, VS5 and VS12
These pins are used to monitor the main power outputs.
The internal circuitry of the NCP112 provides over and
undervoltage detection and indicates an error state. The
over and undervoltage levels meet the ATX specification.
In order to avoid unexpected oscillation of the device, the
NCP112 features both over and undervoltage hysteresis.
The overvoltage detection circuitry incorporates a fault
delay, which helps to filter short positive voltage spikes
below 100 ms. To avoid triggering a false undervoltage
signal during power−up, a timing capacitor (CTUV) may
be used to introduce a user defined blanking delay.
Additional Overvoltage Protection – ADJ
This pin can be used as another user−defined monitoring
input and has a hysteresis feature similar to VS33, VS5 and
VS12. When the input voltage is below the threshold level
of 1.28 V, a fault condition is asserted. Note that the ADJ
pin is logically ORed with the overvoltage detector output,
thus there is a 100 ms fault delay.
Power Good Input – PGI
The Power Good Input (PGI) can be used to monitor an
additional logic event, for example, the temperature inside
an ATX power supply unit. When the input voltage at the
PGI input is below the threshold level of 1.28 V, the Power
Good Output (PGO) signal remains in a low state, even if
all three sense inputs are within voltage limits. The PGI
signal, along with the REMOTE, and the over and
undervoltage singles encounter a power good delay circuit
as depicted in Figure 1.
Timing Capacitors – CTUV, CTREMOTE, CTPG
The NCP112 timing circuitry is optimized for utilizing
low cost, 100 nF ceramic capacitors. The time delays of
CTUV, CTREMOTE, and CTPG can be adjusted by simply
changing external capacitor values. The time delay is a
linear function of the capacitance because the NCP112 uses
internal current sources for charging and/or discharging
capacitors.
Remote Control – REMOTE
A reset signal can be realized with the REMOTE pin.
When the Remote pin is in the active low state, the external
link (the Fault signal) between the NCP112 and the Pulse
Width Modulator (PWM) generator of the external power
supply is enabled (Figure 3). In order to effectively reset
the latch, a minimum width remote pulse should be
applied. The width of this pulse should be greater than
T
REM
, which is determined by adding an external capacitor
(CTREMOTE). Note that the REMOTE pin is internally
pulled up to 3.4 V.
Power Good Output – PGO
The purpose of the PGO function is to warn the
motherboard that the voltage of at least one of the three
main power lines is out of range, independent of the ADJ
input. Please refer to Table 1 for a functional Truth table.
The PGO is subject to a delay T
PG
, which can be adjusted
with an external capacitor (CTPG). The Power Good
Output pin is capable of sinking 20 mA of current.
Fault Output – FAULT
In a typical application such as Figure 3, the fault pin
(FAULT), is activated when any one of the three main
power lines (3.3 V, 5.0 V, 12 V) is out of range or the ADJ
pin is below 1.28 V. This is independent of the PGI input.
The Fault output is the external link between the NCP112
and the primary PWM. In the event of a short circuit
condition, the overvoltage circuitry provides an additional
delay time T
FAULT
which provides adequate protection.
Voltage Reference – VREF
The VREF is a 2.5V precision reference output, with
current sourcing capability of 20 mA. No bypass capacitor
or minimum output current is required to maintain stability.
ORDERING INFORMATION
Device Package Shipping
†
NCP112PG PDIP−14
(Pb−Free)
25 Units / Rail
NCP112DG SOIC−14
(Pb−Free)
55 Units / Rail
NCP112DR2G SOIC−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
