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LTC3822EDD-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC3822-1
10
38221f
signal goes low and the controller resumes normal opera-
tion by turning on the top N-channel MOSFET on the next
cycle of the internal oscillator.
When the controller is enabled for Burst Mode or pulse
skipping operation, the inductor current is not allowed to
reverse. Hence, the controller operates discontinuously.
The reverse current comparator RICMP senses the drain-
to-source voltage of the bottom N-channel MOSFET. This
MOSFET is turned off just before the inductor current
reaches zero, preventing it from going negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the I
TH
pin. The top MOSFET is turned on
every cycle (constant frequency) regardless of the I
TH
pin
voltage. In this mode, the effi ciency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and no noise at
audio frequencies.
When the SYNC/MODE pin is clocked by an external clock
source to use the phase-locked loop (see Frequency Selec-
tion and Phase-Locked Loop), or is set to a DC voltage
between 0.4V and several hundred mV below V
IN
, the
LTC3822-1 operates in PWM pulse skipping mode at light
loads. In this mode, the current comparator ICMP may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles. The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode op-
eration. However, it provides low current effi ciency higher
than forced continuous mode, but not nearly as high as
Burst Mode operation. During start-up or an undervoltage
condition (V
FB
≤ 0.54V), the LTC3822-1 operates in pulse
skipping mode (no current reversal allowed), regardless
of the state of the SYNC/MODE pin.
Short-Circuit Protection
The LTC3822-1 monitors V
FB
to detect a short-circuit
on V
OUT
. When V
FB
is near ground, switching frequency
is reduced to prevent the inductor current from running
away. The oscillator frequency will progressively return
to normal when V
FB
rises above ground. This feature is
disabled during start-up.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OVP)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V
FB
pin has risen 13.33%
above the reference voltage of 0.6V, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage is cleared.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3822-1’s controllers
can be selected using the PLLLPF pin. If the SYNC/MODE
is not being driven by an external clock source, the PLLLPF
can be fl oated, tied to V
IN
or tied to GND to select 550kHz,
750kHz or 300kHz, respectively.
A phase-locked loop (PLL) is available on the LTC3822-1
to synchronize the internal oscillator to an external clock
source that connects to the SYNC/MODE pin. In this case,
a series RC should be connected between the PLLLPF pin
and GND to serve as the PLL’s loop fi lter. The LTC3822-1
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the top MOSFET to the rising edge of
the synchronizing signal.
The typical capture range of the LTC3822-1’s phase-locked
loop is from approximately 200kHz to 1MHz.
Boost Capacitor Refresh Timeout
In order to maintain suffi cient charge on C
B
, the converter
will briefl y turn off the top MOSFET and turn on the bottom
MOSFET if at any time the bottom MOSFET has remained
off for 10 cycles. This most commonly occurs in a dropout
situation where V
IN
is close to V
OUT
.
OPERATION
(Refer to Functional Diagram)
LTC3822-1
11
38221f
Undervoltage Lockout
To prevent operation of the MOSFETs below safe input
voltage levels, an undervoltage lockout is incorporated
in the LTC3822-1. When the input supply voltage (V
IN
)
drops below 2.25V, the external MOSFETs and all internal
circuits are turned off except for the undervoltage block,
which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG Pin)
When the LTC3822-1 controller is operating below 20%
duty cycle, the peak current sense voltage (between the
V
IN
and SENSE
–
/SW pins) allowed across the external top
MOSFET is determined by:
∆≈VA
VV
SENSE MAX
ITH
()
•
–.07
10
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to
V
IN
selects A = 5/3; tying IPRG to GND selects A = 2/3.
The maximum value of V
ITH
is typically about 1.98V, so
the maximum sense voltage allowed across the external
main MOSFET is 125mV, 200mV or 82mV for the three
respective states of the IPRG pin.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor (SF) given by the
curve in Figure 1.
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the main MOSFET:
I
V
R
PK
SENSE MAX
DS ON
=
∆
()
()
If a sense resistor is used, ΔV
SENSE(MAX)
is the peak cur-
rent sense voltage (between the V
IN
and SENSE
–
/SW pins)
across the sense resistor. The peak inductor is determined
by the peak sense voltage and the resistance of the sense
resistor:
I
V
R
PK
SENSE MAX
SENSE
=
∆
()
Power Good (PGOOD) Pin (GN Only)
A window comparator monitors the feedback voltage and
pulls the open-drain PGOOD output pin low when the
feedback voltage is not within ±10% of the 0.6V reference
voltage. PGOOD is low when the LTC3822-1 is shut down
or in undervoltage lockout.
OPERATION
(Refer to Functional Diagram)
DUTY CYCLE (%)
10
SF = I/I
MAX
(%)
60
80
110
100
90
38221 F01
40
20
50
70
90
30
10
0
30
50
70
200
40
60
80
100
Figure 1. Maximum Peak Current vs Duty Cycle
LTC3822-1
12
38221f
APPLICATIONS INFORMATION
The typical LTC3822-1 application circuit is shown on
the front page of this data sheet. External component
selection for the controller is driven by the load require-
ment and begins with the selection of the inductor and
the power MOSFETs.
Power MOSFET Selection
The LTC3822-1’s controller requires external N-chan-
nel power MOSFETs for the topside (main) and bottom
(synchronous) switches. The main selection criteria for
the power MOSFETs are the breakdown voltage V
BR(DSS)
,
threshold voltage V
GS(TH)
, on-resistance R
DS(ON)
, reverse
transfer capacitance C
RSS
, turn-off delay t
D(OFF)
and the
total gate charge Q
G
.
The gate drive voltage is usually the input supply voltage.
Since the LTC3822-1 is designed for operation at low input
voltages, a sublogic level MOSFET (R
DS(ON)
guaranteed at
V
GS
= 2.5V) is required.
The topside MOSFET’s on-resistance is chosen based on
the required load current. The maximum average load
current I
OUT(MAX)
is equal to the peak inductor current
minus half the peak-to-peak ripple current I
RIPPLE
. The
LTC3822-1’s current comparator monitors the drain-to-
source voltage V
DS
of the top MOSFET, which is sensed
between the V
IN
and SW pins. The peak inductor current
is limited by the current threshold, set by the voltage on
the I
TH
pin, of the current comparator. The voltage on the
I
TH
pin is internally clamped, which limits the maximum
current sense threshold ΔV
SENSE(MAX)
to approximately
125mV when IPRG is fl oating (82mV when IPRG is tied
low; 200mV when IPRG is tied high).
The output current that the LTC3822-1 can provide is
given by:
I
V
R
I
OUT MAX
SENSE MAX
DS ON
RIPPLE
()
()
()
–=
∆
2
where I
RIPPLE
is the inductor peak-to-peak ripple current
(see Inductor Value Calculation).
A reasonable starting point is setting ripple current I
RIPPLE
to be 40% of I
OUT(MAX)
. Rearranging the above equation
yields:
R
V
I
DS ON MAX
SENSE MAX
OUT MAX
()
()
()
•=
5
6
∆
for DutyyCycle<20%
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of R
DS(ON)
to provide the required
amount of load current:
RSF
V
I
DS ON MAX
SENSE MAX
OUT MAX
()
()
()
••=
5
6
∆
where SF is a scale factor whose value is obtained from
the curve in Figure 1.
These must be further derated to take into account the
signifi cant variation in on-resistance with temperature. The
following equation is a good guide for determining the re-
quired R
DS(ON)MAX
at 25°C (manufacturer’s specifi cation),
allowing some margin for variations in the LTC3822-1 and
external component values:
RSF
V
I
DS ON MAX
SENSE MAX
OUT MAX
()
()
()
•.• •
•
=
5
6
09
∆
ρρ
T
The ρ
T
is a normalizing term accounting for the temperature
variation in on-resistance, which is typically about 0.4%/°C,
as shown in Figure 2. Junction-to-case temperature ΔT
JC
is about 10°C in most applications. For a maximum ambi-
ent temperature of 70°C, using ρ
80°C
≈ 1.3 in the above
equation is a reasonable choice.
The power dissipated in the MOSFETs strongly depends
on their respective duty cycles and load current. When
the LTC3822-1 is operating in continuous mode, the duty
cycles for the MOSFETs are:
Top MOSFET Duty Cycle =
V
OUT
V
Bottom MOSFET
IN
–
Duty Cycle
VV
V
IN OUT
IN
=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC3822EDD-1

Mfr. #:
Buy LTC3822EDD-1
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators LTC3822-1 - No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller
Lifecycle:
New from this manufacturer.
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