Table 13: DDR2 I
DD
Specifications and Conditions – 1GB
Values shown for MT47H128M16 DDR2 SDRAM only and are computed from values specified in the 2Gb (128 Meg x 16)
component data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD0
600 540 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL = CL
(I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
DD4W
I
DD1
720 640 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is LOW;
Other control and address bus inputs are stable; Data bus inputs are floating
I
DD2P
48 48 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
DD2Q
300 260 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S# is
HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-
ing
I
DD2N
320 280 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
180 160 mA
Slow PDN exit
MR[12] = 1
56 56
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs are switching
I
DD3N
340 300 mA
Operating burst write current: All device banks open; Continuous burst writes; BL
= 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
I
DD4W
1080 1000 mA
Operating burst read current: All device banks open; Continuous burst read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
I
DD4R
1180 1100 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
I
DD5
1200 1120 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
I
DD6
48 48 mA
Operating bank interleave read current: All device banks interleaving reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are switch-
ing
I
DD7
1780 1580 mA
256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM
I
DD
Specifications
PDF: 09005aef83c05a5d
htf4c32_64_128x64hz.pdf - Rev. C 9/10 EN
13
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