6.42
6
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE
1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6. I/O
8 - I/O15 for IDT70V9289.
7. I/O
0 - I/O7 for IDT70V9289.
Truth Table I—Read/Write and Enable Control
(1,2,3)
Pin Names
Left Port Right Port Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip Enables
(3)
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
15L
A
0R
- A
15R
Address
I/O
0L
- I/O
17L
(1)
I/O
0R
- I/O
17R
(1)
Data Input/Output
CLK
L
CLK
R
Clock
UB
L
UB
R
Upper Byte Select
(2)
LB
L
LB
R
Lower Byte Select
(2)
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
DD
Power (3.3V)
V
SS
Ground (0V)
4856 tbl 01
OE
CLK
CE
0
(5)
CE
1
(5)
UB
(4)
LB
(4)
R/W
Upper Byte
I/O
9-17
(6)
Lower Byte
I/O
0-8
(7)
MODE
X
↑
H X X X X High-Z High-Z Deselected–Power Down
X
↑
X L X X X High-Z High-Z Deselected–Power Down
X
↑
L H H H X High-Z High-Z Both Bytes Deselected
X
↑
LHLHL D
IN
High-Z Write to Upper Byte Only
X
↑
LHHLL High-Z DATA
IN
Write to Lower Byte Only
X
↑
LHLLL DATA
IN
DATA
IN
Write to Both Bytes
L
↑
LHLHH DATA
OUT
High-Z Read Upper Byte Only
L
↑
LHHLH High-Z DATA
OUT
Read Lower Byte Only
L
↑
LHLLH DATA
OUT
DATA
OUT
Read Both Bytes
H X L H L L X High-Z High-Z Outputs Disabled
4856 tbl 02
NOTES:
1. I/O
0X - I/O15X for IDT70V9289.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE
1 are single buffered when FT/PIPE = VIL,
CEo and CE
1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.