74HC259D
1
CMOS Digital Integrated Circuits Silicon Monolithic
74HC259D
74HC259D
74HC259D
74HC259D
Start of commercial production
2016-05
1.
1.
1.
1. Functional Description
Functional Description
Functional Description
Functional Description
• 8-Bit Addressable Latch
2.
2.
2.
2. General
General
General
General
The 74HC259D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C
2
MOS technology.
It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable
input G is held low, the data is written into the bit selected by address inputs, the other bit hold their previous
conditions.
When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous
condition are held. When CLEAR is held low and G is held high, all bits are resent to low regardless of the other
inputs. When both of CLEAR and G held low, all bits which isn't selected by adress inputs are resent to low.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3.
3.
3.
3. Features
Features
Features
Features
(1) High speed: t
pd
= 15 ns (typ.) at V
CC
= 5 V
(2) Low power dissipation: I
CC
= 4.0 µA (max) at T
a
= 25
(3) Balanced propagation delays: t
PLH
≈ t
PHL
(4) Wide operating voltage range: V
CC(opr)
= 2.0 to 6.0 V
4.
4.
4.
4. Packaging
Packaging
Packaging
Packaging
2016-08-04
Rev.3.0
©2016 Toshiba Corporation
