1. General description
The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop
and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. It is a low-voltage Si-gate CMOS device
and is pin and functionally compatible with the 74HC574 and 74HCT574.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
n Wide operating voltage: 1.0 V to 5.5 V
n Optimized for low voltage applications: 1.0 V to 3.6 V
n Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
n Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
n Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Common 3-state output enable input
n Multiple package options
n Specified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Ordering information
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 04 — 14 May 2009 Product data sheet
Table 1. Ordering information
Type
number
Package
Temperature range Name Description Version
74LV574N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV574D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LV574DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74LV574PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
