ADP3419JRM-REEL Datasheet ADP3419JRMZ-REEL, ADP3419JRM-REEL | P7-P9

ADP3419

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Theory of Operation

The ADP3419 is a dual MOSFET driver optimized for

driving two N-channel MOSFETs in a synchronous buck

converter topology. A single PWM input signal is all that is

required to properly drive the high-side and the low-side

MOSFETs. Each driver is capable of driving a 3 nF load at

speeds up to 1 MHz. A more detailed description of the

ADP3419 and its features follows. Refer to the detailed

block diagram in Figure 16.

Figure 16. Detailed Block Diagram of the ADP3419

ADP3419

VCC

CROWBAR

VCC

BST

DRVH

GND

DRVL

UVLO

AND BIAS

OVERLAP

PROTECTION

AND

TIME−OUT

CIRCUIT

BST

DCIN

DRVLSD

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit holds both

MOSFET driver outputs low during VCC supply ramp-up.

The UVLO logic becomes active and in control of the driver

outputs at a supply voltage of no greater than 1.5 V. The

UVLO circuit waits until the VCC supply has reached a

voltage high enough to bias logic level MOSFETs fully on

before releasing control of the drivers to the control pins.

Driver Control Input

The driver control input (IN) is connected to the duty ratio

modulation signal of a switch-mode controller. IN can be

driven by 2.5 V to 5.0 V logic. The output MOSFETs are

driven so that the SW node follows the polarity of IN.

Low-Side Driver

The low-side driver is designed to drive a

ground-referenced low R

DS(ON)

N-channel synchronous

rectifier MOSFET. The bias to the low-side driver is

internally connected to the VCC supply and GND. Once the

supply voltage ramps up and exceeds the UVLO threshold,

the driver is enabled. When the driver is enabled, the driver’s

output is 180° out of phase with the IN pin. Table 2 shows

the relationship between DRVL and the different control

inputs of the ADP3419.

High-Side Driver

The high-side driver is designed to drive a floating low

DS(ON)

N-channel MOSFET. The bias voltage for the

high-side driver is developed by an external bootstrap supply

circuit, which is connected between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

capacitor, C

BST

. When the ADP3419 is starting up, the SW

pin is at ground, so the bootstrap capacitor charges up to

VCC through D1. Once the supply voltage ramps up and

exceeds the UVLO threshold, the driver is enabled. When IN

goes high, the high-side driver begins to turn on the

high-side MOSFET (Q1) by transferring charge from C

BST

As Q1 turns on, the SW pin rises up to V

DCIN

, forcing the

BST pin to V

DCIN

+ V

C(BST)

, which is enough

gate-to-source voltage to hold Q1 on. To complete the cycle,

Q1 is switched off by pulling the gate down to the voltage at

the SW pin. When the low-side MOSFET (Q2) turns on, the

SW pin is pulled to ground. This allows the bootstrap

capacitor to charge up to VCC again.

When the driver is enabled, the driver’s output is in phase

with the IN pin. Table 2 shows the relationship between

DRVH and the different control inputs of the ADP3419.

Overlap Protection Circuit

The overlap protection circuit prevents both main power

switches, Q1 and Q2, from being on at the same time. This

is done to prevent shoot-through currents from flowing

through both power switches and the associated losses that

can occur during their on-off transitions. The overlap

protection circuit accomplishes this by adaptively

controlling the delay from Q1’s turn-off to Q2’s turn-on, and

the delay from Q2’s turn-off to Q1’s turn-on.

To prevent the overlap of the gate drives during Q1’s

turn-off and Q2’s turn-on, the overlap circuit monitors the

voltage at the SW pin and DRVH pin. When IN goes low, Q1

begins to turn off. The overlap protection circuit waits for

the voltage at the SW and DRVH pins to both fall below

1.6 V. Once both of these conditions are met, Q2 begins to

turn on. Using this method, the overlap protection circuit

ensures that Q1 is off before Q2 turns on, regardless of

variations in temperature, supply voltage, gate charge, and

drive current. There is, however, a timeout circuit that

overrides the waiting period for the SW and DRVH pins to

reach 1.6 V. After the timeout period has expired, DRVL is

asserted high regardless of the SW and DRVH voltages. In

the opposite case, when IN goes high, Q2 begins to turn off

after a propagation delay. The overlap protection circuit

waits for the voltage at DRVL to fall below 1.6 V, after which

DRVH is asserted high and Q1 turns on.

Low-Side Driver Shutdown

The low-side driver shutdown DRVLSD allows a control

signal to shut down the synchronous rectifier. Under light

load conditions, DRVLSD

should be pulled low before the

polarity reversal of the inductor current to maximize light

load conversion efficiency. DRVLSD

can also be pulled low

for reverse voltage protection purposes.

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When DRVLSD is low, the low-side driver stays low.

When DRVLSD

is high, the low-side driver is enabled and

controlled by the driver signals, as previously described.

Low-Side Driver Timeout

In normal operation, the DRVH signal tracks the IN signal

and turns off the Q1 high-side switch with a few 10 ns delay

pdlDRVH

) following the falling edge of the input signal.

When Q1 is turned off, DRVL is allowed to go high, Q2 turns

on, and the SW node voltage collapses to zero. But in a fault

condition such as a high-side Q1 switch drain-source short

circuit, the SW node cannot fall to zero, even when DRVH

goes low. The ADP3419 has a timer circuit to address this

scenario. Every time the IN goes low, a DRVL on-time delay

timer is triggered. If the SW node voltage does not trigger a

low-side turn-on, the DRVL on-time delay circuit does it

instead, when it times out with t

SW(TO)

delay. If Q1 is still

turned on, that is, its drain is shorted to the source, Q2 turns

on and creates a direct short circuit across the V

DCIN

voltage

rail. The crowbar action causes the fuse in the V

DCIN

current

path to open. The opening of the fuse saves the load (CPU)

from potential damage that the high-side switch short circuit

could have caused.

Crowbar Function

In addition to the internal low-side drive time-out circuit,

the ADP3419 includes a CROWBAR input pin to provide a

means for additional overvoltage protection. When

CROWBAR goes high, the ADP3419 turns off DRVH and

turns on DRVL. The crowbar logic overrides the overlap

protection circuit, the shutdown logic, the DRVLSD

logic,

and the UVLO protection on DRVL. Thus, the crowbar

function maximizes the overvoltage protection coverage in

the application. The CROWBAR can be either driven by the

CLAMP pin of buck controllers, such as the ADP3422,

ADP3203, ADP3204, or ADP3205, or controlled by an

independent overvoltage monitoring circuit.

Table 1. ADP3419 Truth Table

CROWBAR UVLO SD DRVLSD IN DRVH DRVL

L L H H H H L

L L H H L L H

L L H L H H L

L L H L L L L

L L L * * L L

L H * * * L L

H L * * * L H

H H * * * L H

* = Don’t Care.

Application Information

Supply Capacitor Selection

For the supply input (VCC) of the ADP3419, a local

bypass capacitor is recommended to reduce the noise and to

supply some of the peak currents drawn. Use a 10 mF or

4.7 mF multilayer ceramic (MLC) capacitor. MLC

capacitors provide the best combination of low ESR and

small size, and can be obtained from the following vendors.

Table 2.

Vendor Part Number Web Address

Murata GRM235Y5V106Z16 www.murata.com

Taiyo-Yuden EMK325F106ZF www.t-yuden.com

Tokin C23Y5V1C106ZP www.tokin.com

Keep the ceramic capacitor as close as possible to the ADP3419.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

BST

) and a Schottky diode (D1), as shown in Figure 16.

Selection of these components can be done after the

high-side MOSFET has been chosen. The bootstrap

capacitor must have a voltage rating that is able to handle at

least 5.0 V more than the maximum supply voltage. The

capacitance is determined by:

BST

HSGATE

BST

(eq. 1)

where:

HSGATE

is the total gate charge of the high-side MOSFET.

BST

is the voltage droop allowed on the high-side

MOSFET drive.

For example, two IRF7811 MOSFETs in parallel have a

total gate charge of about 36 nC. For an allowed droop of

100 mV, the required bootstrap capacitance is 360 nF. A

good quality ceramic capacitor should be used, and derating

for the significant capacitance drop of MLCs at high

temperature must be applied. In this example, selection of

470 nF or even 1 mF would be recommended.

A Schottky diode is recommended for the bootstrap diode

due to its low forward drop, which maximizes the drive

available for the high-side MOSFET. The bootstrap diode

must also be able to handle at least 5.0 V more than the

maximum battery voltage. The average forward current can

be estimated by:

F(AVG)

+ Q

HSGATE

MAX

(eq. 2)

where f

MAX

is the maximum switching frequency of the

controller.

Power and Thermal Considerations

The major power consumption of the ADP3419-based

driver circuit is from the dissipation of MOSFET gate

charge. It can be estimated as:

MAX

[ VCC (Q

HSGATE

) Q

LSGATE

) f

MAX

(eq. 3)

where:

VCC is the supply voltage 5.0 V.

MAX

is the highest switching frequency.

HSGATE

and Q

LSGATE

are the total gate charge of high-side

and low-side MOSFETs, respectively.

For example, the ADP3419 drives two IRF7821 high-side

MOSFETs and two IRF7832 low-side MOSFETs. According

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to the MOSFET data sheets, Q

HSGATE

= 18.6 nC and

LSGATE

= 68 nC. Given that f

MAX

is 300 kHz, P

MAX

would

be about 130 mW.

Part of this power consumption generates heat inside the

ADP3419. The temperature rise of the ADP3419 against its

environment is estimated as:

DT [ q

MAX

(eq. 4)

where θ

is ADP3419’s thermal resistance from junction

to air, given in the absolute maximum ratings as 220°C/W

for a 4−layer board.

The total MOSFET drive power dissipates in the output

resistance of ADP3419 and in the MOSFET gate resistance

as well. η represents the ratio of power dissipation inside the

ADP3419 over the total MOSFET gate driving power. For

normal applications, a rough estimation for η is 0.7. A more

accurate estimation can be calculated using:

h [

HSGATE

) Q

LSGATE

0.5 R1

R1 ) R

HSGATE

) R

)

0.5 R2

R2 ) R

HSGATE

(eq. 5)

)

LSGATE

HSGATE

) Q

LSGATE

0.5 R3

R3 ) R

LSGATE

)

0.5 R4

R4 ) R

LSGATE

where:

R1 and R2 are the output resistances of the high-side driver:

R1 = 1.7 (DRVH − BST), R2 = 0.8 (DRVH − SW).

R3 and R4 are the output resistances of the low-side driver:

R3 = 1.7 (DRVL − VCC), R4 = 0.8 (DRVL − GND).

R is the external resistor between the BST pin and the BST

capacitor.

HSGATE

and R

LSGATE

are gate resistances of high-side and

low-side MOSFETs, respectively.

Assuming that R = 0 and that R

HSGATE

= R

LSGATE

= 0.5,

Equation 5 gives a value of η = 0.71. Based on Equation 4,

the estimated temperature rise in this example is about 22°C.

PC Board Layout Considerations

Use the following general guidelines when designing

printed circuit boards. Figure 17 gives an example of the

typical land patterns based on the guidelines given here.

• The VCC bypass capacitor should be located as close as

possible to the VCC and GND pins. Place the

ADP3419 and bypass capacitor on the same layer of the

board, so that the PCB trace between the ADP3419

VCC pin and the MLC capacitor does not contain any

via. An ideal location for the bypass MLC capacitor is

near Pin 5 and Pin 6 of the ADP3419.

• High frequency switching noise can be coupled into the

VCC pin of the ADP3419 via the BST diode.

Therefore, do not connect the anode of the BST diode

to the VCC pin with a short trace. Use a separate via or

trace to connect the anode of the BST diode directly to

the VCC 5.0 V power rail.

• It is best to have the low-side MOSFET gate close to

the DRVL pin; otherwise, use a short and very thick

PCB trace between the DRVL pin and the low-side

MOSFET gate.

• Fast switching of the high-side MOSFET can reduce

switching loss. However, EMI problems can arise due

to the severe ringing of the switch node voltage.

Depending on the character of the low-side MOSFET, a

very fast turn-on of the high-side MOSFET may falsely

turn on the low-side MOSFET through the dv/dt

coupling of its Miller capacitance. Therefore, when fast

turn-on of the high-side MOSFET is not required by the

application, a resistor of about 1 W to 2 W can be placed

between the BST pin and the BST capacitor to limit the

turn-on speed of the high-side MOSFET.

Figure 17. External Component Placement Example

VCC

BST

SHORT, THICK TRACE

TO THE GATES OF

LOW-SIDE MOSFETS

TO SWITCH

NODE

ORDERING INFORMATION

Device Number Branding Package Type Shipping

†

ADP3419JRM−REEL P9A 10−Lead MSOP 3000 Tape & Reel

ADP3419JRMZ−REEL P9B 10−Lead MSOP 3000 Tape & Reel

ADP34190091RMZR P9B 10−Lead MSOP 3000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*The “Z’’ suffix indicates Pb−Free part.

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