MAX1264BCEG+ Datasheet MAX1264BEEG+, MAX1264AEEG+, MAX1262BEEI+ | P13-P15

Internal Clock Mode

Select internal clock mode to release the µP from the

burden of running the SAR conversion clock. To select

this mode, bit D7 of the control byte must be set to 1

and bit D6 must be set to 0; the internal clock frequency

is then selected, resulting in a 3.6µs conversion time.

When using the internal clock mode, connect the CLK

pin either high or low to prevent the pin from floating.

External Clock Mode

To select the external clock mode, bits D6 and D7 of

the control byte must be set to 1. Figure 6a shows the

clock and WR timing relationship for internal and exter-

nal (Figure 6b) acquisition modes with an external

clock. Proper operation requires a 100kHz to 7.6MHz

clock frequency with 30% to 70% duty cycle. Operating

the MAX1262/MAX1264 with clock frequencies lower

than 100kHz is not recommended, because it causes a

voltage droop across the hold capacitor in the T/H

stage that results in degraded performance.

MAX1262/MAX1264

400ksps, +5V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 13

CLK

WR GOES HIGH WHEN CLK IS HIGH.

WR GOES HIGH WHEN CLK IS LOW.

CWS

CWH

ACQUISITION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQMOD = 0

Figure 6a. External Clock and

Timing (Internal Acquisition Mode)

CLK

WR GOES HIGH WHEN CLK IS HIGH.

WR GOES HIGH WHEN CLK IS LOW.

CWH

CWS

ACQUISITION STARTS

CONVERSION STARTS

ACQUISITION ENDS

ACQMOD = 1

ACQMOD = "0"

Figure 6b. External Clock and

Timing (External Acquisition Mode)

MAX1262/MAX1264

Digital Interface

Input (control byte) and output data are multiplexed on

a tri-state parallel interface. This parallel interface (I/O)

can easily be interfaced with standard µPs. Signals CS,

WR, and RD control the write and read operations. CS

represents the chip-select signal, which enables a µP

to address the MAX1262/MAX1264 as an I/O port.

When high, CS disables the CLK, WR, and RD inputs

and forces the interface into a high-impedance (high-Z)

state.

Input Format

The control byte is latched into the device on pins D7–

D0 during a write command. Table 2 shows the control

byte format.

Output Format

The output format for the MAX1262/MAX1264 is binary in

unipolar mode and two’s complement in bipolar mode.

When reading the output data, CS and RD must be low.

When HBEN = 0, the lower 8 bits are read. With HBEN =

1, the upper 4 bits are available and the output data bits

D7–D4 are set either low in unipolar mode or to the value

of the MSB in bipolar mode (Table 5).

400ksps, +5V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

14 ______________________________________________________________________________________

Table 2. Control Byte Format

Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)

Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)

*Channels CH4–CH7 apply to MAX1262 only.

*Channels CH4

–CH7 apply to MAX1262 only.

A1 CH0

0 +0 -0

0 -1

CH2 CH4*

1 0 + -

CH3

CH1 CH7*CH6*

CH5*

1 - +0

0 0

+ -1

0 1 - +1

1 0 -1

1 1

1 +-

A1 CH0

0 +00

0 1

CH2 CH4*

1 0 +

CH3

CH1 CH7*

CH6*

COM

CH5*

1 + -0

0 0

0 1 +1

1 01

1 1

+ -

D6 D4

PD0

SGL/DIF

ACQMOD A2 A0A1

UNI/BIP

PD1

D5 D2 D0 (LSB)D1D3D7 (MSB)

___________Applications Information

Power-On Reset

When power is first applied, internal power-on reset cir-

cuitry activates the MAX1262/MAX1264 in external

clock mode and sets INT high. After the power supplies

stabilize, the internal reset time is 10µs, and no conver-

sions should be attempted during this phase. When

using the internal reference, 500µs are required for

REF

to stabilize.

Internal and External Reference

The MAX1262/MAX1264 can be used with an internal

or external reference voltage. An external reference

can be connected directly to REF or REFADJ.

An internal buffer is designed to provide +2.5V at REF

for both devices. The internally trimmed +1.22V refer-

ence is buffered with a +2.05V/V gain.

Internal Reference

The full-scale range with the internal reference is +2.5V

with unipolar inputs and ±1.25V with bipolar inputs. The

internal reference buffer allows for small adjustments

(±100mV) in the reference voltage (Figure 7).

Note: The reference buffer must be compensated with

an external capacitor (4.7µF min) connected between

REF and GND to reduce reference noise and switching

spikes from the ADC. To further minimize reference

noise, connect a 0.01µF capacitor between REFADJ

and GND.

External Reference

With the MAX1262/MAX1264, an external reference can

be placed at either the input (REFADJ) or the output

(REF) of the internal reference-buffer amplifier.

Using the REFADJ input makes buffering the external

reference unnecessary. The REFADJ input impedance

is typically 17kΩ.

When applying an external reference to REF, disable

the internal reference buffer by connecting REFADJ to

. The DC input resistance at REF is 25kΩ.

Therefore, an external reference at REF must deliver up

to 200µA DC load current during a conversion and

have an output impedance less than 10Ω. If the refer-

ence has higher output impedance or is noisy, bypass

it close to the REF pin with a 4.7µF capacitor.

Power-Down Modes

To save power, place the converter in a low-current

shutdown state between conversions. Select standby

mode or shutdown mode using bits D6 and D7 of the

control byte (Tables 1 and 2). In both software power-

down modes, the parallel interface remains active, but

the ADC does not convert.

Standby Mode

While in standby mode, the supply current is 1mA (typ).

The part powers up on the next rising edge on WR and

is ready to perform conversions. This quick turn-on time

allows the user to realize significantly reduced power

consumption for conversion rates below 400ksps.

Shutdown Mode

Shutdown mode turns off all chip functions that draw

quiescent current, reducing the typical supply current

to 2µA immediately after the current conversion is com-

pleted. A rising edge on WR causes the MAX1262/

MAX1264 to exit shutdown mode and return to normal

operation. To achieve full 12-bit accuracy with a 4.7µF

reference bypass capacitor, 500µs is required after

power-up. Waiting 500µs in standby mode instead of in

full-power mode can reduce power consumption by a

factor of 3 or more. When using an external reference,

MAX1262/MAX1264

400ksps, +5V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

______________________________________________________________________________________ 15

Table 5. Data-Bus Output (8 + 4 Parallel

Interface)

= +5V

330kΩ

50kΩ

GND

50kΩ

0.01µF

4.7µF

REFADJ

REF

MAX1262

MAX1264

Figure 7. Reference Voltage Adjustment with External

Potentiometer

PIN HBEN = 0 HBEN = 1

D0 Bit 0 (LSB) Bit 8

D1 Bit 1 Bit 9

D2 Bit 2 Bit 10

D3 Bit 3 Bit 11 (MSB)

BIPOLAR

(UNI/BIP = 0)

UNIPOLAR

(UNI/BIP = 1)

D4 Bit 4 Bit 11 0

D5 Bit 5 Bit 11 0

D6 Bit 6 Bit 11 0

D7 Bit 7 Bit 11 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX1264BCEG+

Mfr. #:

Buy MAX1264BCEG+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 4Ch 400ksps 5.5V Precision ADC

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MAX1264BCEG+

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