TMP03/TMP04
–13–
When the READ_TMP04 routine is called, the counter registers
are cleared. The program sets the counters to their 16-bit mode,
and then waits for the TMP04 output to go high. When the
input port returns a logic high level, Timer 0 starts. The timer
continues to run while the program monitors the input port.
When the TMP04 output goes low, Timer 0 stops and Timer 1
starts. Timer 1 runs until the TMP04 output goes high, at which
time the TMP04 interface is complete. When the subroutine
ends, the timer values are stored in their respective SFRs and
the TMP04’s temperature can be calculated in software.
Since the 80C51 operates asynchronously to the TMP04, there
is a delay between the TMP04 output transition and the start
of the timer. This delay can vary between 0 µs and the execution
time of the instruction that recognized the transition. The
80C51’s “jump on port.bit” instructions (JB and JNB) require
24 clock cycles for execution. With a 12 MHz clock, this pro-
duces an uncertainty of 2 µs (24 clock cycles/12 MHz) at each
transition of the TMP04 output. The worst case condition occurs
when T1 is 4 µs shorter than the actual value and T2 is 4 µs
longer. For a 25°C reading (“room temperature”), the nominal
error caused by the 2 µs delay is only about ±0.15°C.
The TMP04 is also easily interfaced to digital signal processors
(DSPs), such as the ADSP210x series. Again, only a single I/O
pin is required for the interface (Figure 11).
D
OUT
TMP04
5V
GND
V+
FI (FLAG IN)
10MHz
n
16-BIT DOWN
COUNTER
CLOCK
OSCILLATOR
ADSP-210x
TIMER
ENABLE
Figure 11. Interfacing the TMP04 to the ADSP-210x Digital
Signal Processor
The ADSP2101 only has one counter, so the interface software
differs somewhat from the 80C51 example. The lack of two
counters is not a limitation, however, because the DSP archi-
tecture provides very high execution speed. The ADSP-2101
executes one instruction for each clock cycle, versus one instruc-
tion for twelve clock cycles in the 80C51, so the ADSP-2101
actually produces a more accurate conversion while using a
lower oscillator frequency.
The timer of the ADSP2101 is implemented as a down counter.
When enabled by means of a software instruction, the counter is
decremented at the clock rate divided by a programmable pres-
caler. Loading the value n – 1 into the prescaler register will
divide the crystal oscillator frequency by n. For the circuit of
Figure 11, therefore, loading 4 into the prescaler will divide the
10 MHz crystal oscillator by 5 and thereby decrement the counter
at a 2 MHz rate. The TMP04 output is ratiometric, of course,
so the exact clock frequency is not important.
A typical software routine for interfacing the TMP04 to the
ADSP2101 is shown in Listing 2. The program begins by initial-
izing the prescaler and loading the counter with 0FFFF
H
. The
ADSP2101 monitors the FI flag input to establish the falling
edge of the TMP04 output, and starts the counter. When the
TMP04 output goes high, the counter is stopped. The
counter value is then subtracted from 0FFFF
H
to obtain the
actual number of counts, and the count is saved. Then the
counter is reloaded and runs until the TMP04 output goes low.
Finally, the TMP04 pulsewidths are converted to temperature
using the scale factor of Equation 1.
Some applications may require a hardware interface for the
TMP04. One such application could be to monitor the tempera-
ture of a high power microprocessor. The TMP04 interface
would be included as part of the system ASIC, so that the micro-
processor would not be burdened with the overhead of timing
the output pulsewidths.
A typical hardware interface for the TMP04 is shown in Figure
12. The circuit measures the output pulsewidths with a resolu-
tion of ±1 µs. The TMP04 T1 and T2 periods are measured
with two cascaded 74HC4520 8-bit counters. The counters,
accumulating clock pulses from the 1 MHz external oscillator,
have a maximum period of 65 ms.
The logic interface is straightforward. On both the rising and
falling edges of the TMP04 output, an exclusive-or gate gener-
ates a pulse. This pulse triggers one half of a 74HC4538 dual
one-shot. The pulse from the one-shot is ANDed with the
TMP04 output polarity to store the counter contents in the
appropriate output registers. The falling edge of this pulse also
triggers the second one-shot, which generates a reset pulse for
the counters. After the reset pulse, the counters will begin to
count the next TMP04 output phase.
As previously mentioned, the counters have a maximum period
of 65 ms with a 1 MHz clock input. However, the TMP04’s T1
and T2 times will never exceed 32 ms. Therefore, the most
s
ignificant bit (MSB) of counter #2 will not go high in nor-
mal operation, and can be used to warn the system that an
error condition (such as a broken connection to the TMP04)
exists.
The circuit of Figure 12 will latch and save both the T1 and T2
times simultaneously. This makes the circuit suitable for debug-
ging or test purposes as well as for a general purpose hardware
interface. In a typical ASIC application, of course, one set of
latches could be eliminated if the latch contents, and the output
polarity, were read before the next phase reversal of the TMP04.
REV. B
