73S8014RN Data Sheet DS_8014RN_014
16 Rev. 1.0
3.5 Card Power Supply
The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO-7816-3
sequencer.
3.6 On-Chip Oscillator and Card Clock
The 73S8014RN devices have an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock
signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be
left unconnected. The 73S8014RN is capable of generating the 4.5, 6.75 and 13.5MHz NDS clock frequencies
using a crystal or external source set at 27MHz.
The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1
and CLKDIV 2, as per the following table:
CLKDIV1 CLKDIV2 CLK Max XTALIN
0 0 1/6 XTALIN 27MHz
0 1 ¼ XTALIN 27MHz
1 0 XTALIN 20MHz
1 1 ½ XTALIN 27MHz
3.7 Activation Sequence
The 73S8014RN smart card interface ICs have an internal 10ms delay on the application of V
DD
where V
DD
>
V
DDF
. No activation is allowed during this 10ms period. The CMDVCC (edge triggered) signal must then be set
low to activate the card. In order to initiate activation, the card must be present; there can be no V
DD
fault.
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets CMDVCC low while the RSTIN is low:
- CMDVCC is set low at t
0
.
- V
CC
will rise to the selected level and then the internal V
CC
control circuit checks the presence of V
CC
at
the end of t
1
. In normal operation, the voltage V
CC
to the card becomes valid before t
1
. If V
CC
is not valid
at t
1
, the OFF goes low to report a fault to the system controller, and V
CC
to the card is shut off.
- Turn I/O to reception mode at t
2
.
- CLK is applied to the card at t
3
.
- RST is a copy of RSTIN after t
3
.
CMDVCC
VCC
I/O
CLK
RSTIN
t
1
t
2
t
3
RST
t
0
t
1
= 0.510 ms (timing by 1.5MHz internal oscillator)
t
2
= 1.5μs, I/O goes to reception state
t
3
= >0.5μs, CLK starts, RST to become the copy of RSTIN
Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low
