MAX1108EUB+T Datasheet MAX1109CUB+, MAX1108CUB+, MAX1109EUB+ | P16-P18

MAX1108/MAX1109

Single-Supply, Low-Power,

2-Channel, Serial 8-Bit ADCs

16 ______________________________________________________________________________________

to the SCLK pin; varying the analog input alters the

result of conversion that is clocked out at the DOUT pin.

A total of 10 clock cycles is required per conversion.

Data Framing

The falling edge of CS does not start a conversion. The

first logic high clocked into DIN is interpreted as a start

bit and defines the first bit of the control byte.

Acquisition starts on the falling edge of the fourth SCLK

and lasts for two SCLKs in external clock mode or four

SCLKs in internal clock mode. Conversion starts imme-

diately after acquisition is completed. The start bit is

defined as:

The first high bit clocked into DIN with CS

low any time the converter is idle; e.g., after

is applied.

In external clock mode, the first high bit

clocked into DIN after the bit 5 (D5) of a con-

version in progress is clocked onto the

DOUT pin.

In internal clock mode, the first high bit

clocked into DIN after the bit 4 (D4) is

clocked onto the DOUT pin.

The MAX1108/MAX1109 can run at a maximum speed

of 10 clocks per conversion. Figure 10 shows the serial-

interface timing necessary to perform a conversion

every 10 SCLK cycles in external clock mode.

Many microcontrollers require that conversions occur in

multiples of 8 SCLK clocks; 16 clocks per conversion is

typically the fastest that a microcontroller can drive the

MAX1108/MAX1109. Figure 11 shows the serial-inter-

face timing necessary to perform a conversion every 16

SCLK cycles in external clock mode.

SCLK

DIN

DOUT

S CONTROL BYTE 0

CONTROL BYTE 1S

CONVERSION RESULT 0

D7 D5 D0

CONVERSION RESULT 1

CONTROL BYTE 2S

8101 10

10 1

ACQ

IDLE

A/D STATE

CONV

Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing

SCLK

DIN

DOUT

S CONTROL BYTE 0

CONTROL BYTE 1S

CONVERSION RESULT 0

D7 D0

CONVERSION RESULT 1

817

Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing

In external clock mode, if CS is toggled before the cur-

rent conversion is complete, the current conversion is

terminated, and the next high bit clocked into DIN is

recognized as a new start bit. This can be useful in

extending acquisition time by selecting conversion on

the same channel with the second control byte (double-

clocking mode), effectively extending acquisition to 6

SCLKs. This technique is ideal if the analog input

source has high impedance, or if it requires more than

1µs to settle; it can also be used to allow the device

and the reference to settle when using power down-

modes (see Power-Down Modes section).

__________Applications Information

Battery Monitoring Mode

This mode of operation samples and converts the mid-

supply voltage, V

/ 2, which is internally generated.

Set SEL2 = SEL1 = SEL0 = 0 in the control byte to

select this configuration. This allows the user to monitor

the condition of a battery providing V

. The reference

voltage must be larger than V

/ 2 for this mode of

operation to work properly. From the result of conver-

sion (CODE), V

is determined as follows:

= CODE · V

REF

/ 128.

Power-On Configuration

When power is first applied, the MAX1108/MAX1109’s

reference is powered down and SHDN is not enabled.

The device needs to be configured by setting CS low

and writing the control byte. Conversion can be started

within 20µs if an external reference is used. When using

the internal reference, allow 12ms for the reference to

settle. This is done by first performing a configuration

conversion to power up the reference and then perform-

ing a second conversion once the reference is settled. No

conversions should be considered correct until the refer-

ence voltage (internal or external) has stabilized.

Power-Down Modes

To save power, place the converter into low-current

power-down mode between conversions. Minimum

power consumption is achieved by programming

REFSHDN = 0 and SHDN = 0 in the input control byte

(Table 4). When software power-down is asserted, it

becomes effective only after the conversion. If the con-

trol byte contains REFSHDN = 0, then the reference will

turn off at the end of conversion. If SHDN = 0, then the

chip will power-down at the end of conversion (in this

mode I/EREF or REFSHDN should also be set to zero).

Table 4 lists the power-down modes of the MAX1108/

MAX1109.

The first logical 1 clocked into DIN after CS falls powers

up the MAX1108/MAX1109 (20µs required for the

device to power up). The reference is powered up only

if internal reference was selected during the previous

conversion. When the reference is powered up after

being disabled, consider the settling time before using

the result of conversion. Typically, 12ms are required

for the reference to settle from a discharge state; less

time may be considered if the external capacitor is not

discharged completely when exiting shutdown. In all

power-down modes, the interface remains active and

conversion results may be read. Use the double clock-

ing technique described in the Data Framing section to

allow more time for the reference to settle before start-

ing a conversion after short power-down.

Voltage Reference

The MAX1108/MAX1109 operate from a single supply

and feature a software-controlled internal reference of

+2.048V (MAX1108) and +4.096V (MAX1109). The

device can operate with either the internal reference or

an external reference applied at the REF pin. See the

Power-Down Modes and Modes of Operation sections

for detailed instructions on reference configuration.

The reference voltage determines the full-scale range:

in unipolar mode, the input range is from 0 to V

REF

; in

bipolar mode, the input range spans RI ±V

REF

/ 2 with

RI = V

REF

/ 2.

MAX1108/MAX1109

Single-Supply, Low-Power,

2-Channel, Serial 8-Bit ADCs

______________________________________________________________________________________ 17

Table 4. Power-Down Modes of the

MAX1108/MAX1109

BIT 2–BIT 0 OF

CONTROL BYTE

1 0

REFSHDN

I/EREF

SHDN

OPERATING MODE

Device Active; Internal refer-

ence powered down after con-

version, powered up at next

start bit.

Device Active/Internal

Reference Active

Device and internal reference

powered down after conversion,

powered up at next start bit.

Device Active/External

Reference Mode

Reserved. Do not use.

Device powered down after

each conversion, powered up

at next start bit. External

Reference Mode.

X = Don’t care

MAX1108/MAX1109

External Reference

To use an external reference, set bit 2 (I/EREF) and bit

1 (REFSHDN) of control byte to 0 and connect the

external reference (V

REF

between 1V and V

) directly

at the REF pin. The DC input impedance at REF is

extremely high, consisting of leakage current only (typi-

cally 10nA). During a conversion, the reference must

be able to deliver up to 20µA average load current and

have an output impedance of 1kΩ or less at the conver-

sion clock frequency. If the reference has higher output

impedance or is noisy, bypass it close to the REF pin

with a 0.1µF capacitor. MAX1109 has an internal refer-

ence of +4.096V. To use the device with supply volt-

ages below 4.5V, external reference mode is required.

With an external reference voltage of less than +2.048V

(MAX1108) or +4.096V (MAX1109) at REF, the increase

in the ratio of the RMS noise to the LSB value (FS / 256)

results in performance degradation and decreased

dynamic range.

Internal Reference

To use the internal reference, set bit 2 (I/EREF) and bit 1

(REFSHDN) of the control byte to 1 and bypass REF with

a 1µF capacitor to ground. The internal reference can be

powered down after a conversion by setting bit 1 (REF-

SHDN) of the control byte to 0. When using the internal

reference, use MAX1108 and MAX1109 with supply volt-

age below 4.5V and above 4.5V, respectively.

Transfer Function

Table 4 shows the full-scale voltage ranges for unipolar

and bipolar modes. Figure 12a depicts the nominal,

unipolar I/O transfer function, and Figure 12b shows the

bipolar I/O transfer function. The zero scale is deter-

mined by the input selection setting and is either COM,

GND, or CH1.

Code transitions occur at integer LSB values. Output

coding is straight binary for unipolar operation and

two’s complement for bipolar operation. With a +2.048V

reference, 1LSB = 8mV (V

REF

/ 256).

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards. Wire-

wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another or run

digital lines underneath the ADC package.

Figure 13 shows the recommended system-ground

connections. A single-point analog ground (star-ground

point) should be established at the A/D ground.

Connect all analog grounds to the star ground. No digi-

tal-system ground should be connected to this point.

The ground return to the power supply for the star

ground should be low impedance and as short as pos-

sible for noise-free operation.

High-frequency noise in the V

power supply may

affect the comparator in the ADC. Bypass the supply to

the star ground with 0.1µF and 1µF capacitors close to

the V

pin of the MAX1108/MAX1109. Minimize

capacitor lead lengths for best supply-noise rejection. If

the power supply is very noisy, a 10Ω resistor can be

connected to form a lowpass filter.

Single-Supply, Low-Power,

2-Channel, Serial 8-Bit ADCs

18 ______________________________________________________________________________________

OUTPUT CODE

FULL-SCALE

TRANSITION

11111111

11111110

11111101

00000011

00000010

00000001

00000000

123

FS - 1LSB

FS = V

REF

+ COM

1LSB = V

REF

256

INPUT VOLTAGE (LSB)

(COM)

Figure 12a. Unipolar Transfer Function

01111111

OUTPUT CODE

01111110

00000010

00000001

00000000

11111111

11111110

11111101

10000001

10000000

-FS

COM

INPUT VOLTAGE (LSB)

+FS -

LSB

+FS =

REF

+ COM

-FS =

-V

REF

+ COM

COM =

REF

1LSB =

REF

256

Figure 12b. Bipolar Transfer Function

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MAX1108EUB+T

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Analog to Digital Converters - ADC 2Ch Single-Supply Low-P Serial 8-Bit

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