STM6524AHARDL6F Datasheet STM6524AUARDL6F, STM6524AHARDL6F, STM6524AUABDL6F | P4-P6

List of figures STM6524

4/24 Doc ID 022335 Rev 3

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Single-button Smart Reset™ typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Dual-button Smart Reset™ typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Option without t

REC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Option with t

REC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Undervoltage condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. Supply current (I

) vs. temperature (T

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Smart Reset™ delay (t

SRC

) vs. temperature (T

), t

SRC

= 7.5 s (typ.). . . . . . . . . . . . . . . . . 13

Figure 11. Test mode entry voltage (V

TEST

) vs. temperature (T

). . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Initial test mode time (t

SRC-INI

) vs. temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. Package outline for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch. . . . . . . . . . . . . . . . . . . . 18

Figure 14. Footprint recommendation for UDFN6 1.6 x 1.3 x 0.55 mm, 0.40 mm pitch. . . . . . . . . . . . 19

Figure 15. Carrier tape for UDFN6 1.6 x 1.3 x 0.55 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. Package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STM6524 Description

Doc ID 022335 Rev 3 5/24

1 Description

The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset

push-button closures do not cause system resets. This is done by implementing extended

Smart Reset™ input delay time (t

SRC

) and combined push-button inputs, which together

ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to distinguish between

a software generated interrupt and a hard system reset. When the input push-buttons are

connected to microcontroller interrupt inputs, and are closed for a short time, the processor

can only be interrupted. If the system still does not respond properly, continuing to keep the

push-buttons closed for the extended setup time t

SRC

causes a hard reset of the processor

through the reset output.

The STM6524 has two combined delayed Smart Reset™ inputs (SR0

, SR1) with preset

delayed Smart Reset™ setup time (t

SRC

). The reset output is asserted after both of the

Smart Reset™ inputs were held active for the selected t

SRC

delay time. Depending on

selected option the RST

output remains asserted either until at least one SR input goes to

inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset

pulse duration is fixed for t

REC

(i.e. factory-programmed). The reset output, RST, is

active low or active high, push-pull or open drain with optional pull-up resistor. The device

fully operates over a broad V

range 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are

ignored and outputs are deasserted; the deasserted reset output levels are then valid down

to 1.0 V.

Test mode

After pull of SR0 up to V

TEST

or more (V

+ 1.4 V, max.) we start counting initial

shorten t

SRC-INI

(42 ms, typ.). After t

SRC-INI

expires, the RST output either goes down for

REC

(if t

REC

option is used) or stays low as long as overvoltage on SR0 in detected (if t

REC

option is not used). This is a feedback and a user knows that the device is locked in the test

mode. Each time both SR

inputs are connected to ground in test mode a shorten

SRC-SHORT

(21 ms, typ.) is used instead of long t

SRC

(0.5 s -10 s). Return from to normal

mode is possible by a new startup of the device (i.e. V

goes to 0 V and back to its original

state). In this way the device can be quickly tested without repeating test mode triggering.

Advantage of this solution is pretty high glitch immunity, feedback to user about entry to the

test mode and testability within full V

range.

Description STM6524

6/24 Doc ID 022335 Rev 3

Figure 1. Logic diagram

Figure 2. Pin connections (top view)

34-

234

'.$

32

32

!-











34-





234

32

!-

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

STM6524AHARDL6F

Mfr. #:

Buy STM6524AHARDL6F

Manufacturer:

STMicroelectronics

Description:

Supervisory Circuits 6-Pin Smart Reset 1.65V to 5.5V 1.5uA

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

STM6524AHARDL6F

STM6524AHARDL6F

Products related to this Datasheet