STM6524 DC and AC parameters
Doc ID 022335 Rev 3 17/24
Table 4. DC and AC characteristic
Symbol Parameter Test conditions
(1)
1. Valid for ambient operating temperature T
A
= -40 to +85 °C, V
CC
= 1.65 to 5.5 V.
Min. Typ.
(2)
2. Typical values are at 25 °C and V
CC
= 3.3 V unless otherwise noted.
Max. Unit
V
CC
Supply voltage
(3)
3. Reset outputs are deasserted below 1.575 V typ. and remain deasserted down to V
CC
= 1 V.
1.65 5.5 V
I
CC
Supply current (inputs in
their inactive state, t
SRC
counter is not running)
V
CC
= 3.0 V 1.1 2.5 µA
V
CC
= 5.0 V 1.5 3.0 µA
V
OL
Reset output voltage low
V
CC
≥
4.5 V, sinking 3.2 mA 0.3 V
V
CC
≥
3.3 V, sinking 2.5 mA 0.3 V
V
CC
≥
1.65 V, sinking 1 mA 0.3 V
V
OH
Reset output voltage high
(push-pull output only)
V
CC
≥
4.5 V, I
SOURCE
= 0.8 mA 0.8 V
CC
V
V
CC
≥
2.7 V, I
SOURCE
= 0.5 mA 0.8 V
CC
V
V
CC
≥
1.65 V, I
SOURCE
= 0.25 mA 0.8 V
CC
V
t
REC
Reset timeout delay,
factory-programmed
(device option)
0.85 1.28 1.71 ms
66 100 134 ms
140 210 280 ms
240 360 480 ms
R
PUO
Internal output pull-up
resistor on RST
(device option) 65 kΩ
I
LO
Output leakage current
V
RST
= 5.5 V, open drain device
option without output pull-up
resistor
-0.1 0.1 µA
Smart Reset
TM
t
SRC
Smart Reset™ delay
T
A
= -40 to +85 °C 0.8 x t
SRC
t
SRC
(4)
4. Factory-programmable in the range of 0.5 s to 10 s typ. in 0.5 s steps (see Table 7 for available delays).
1.2 x t
SRC
s
T
A
= 25 °C 0.9 x t
SRC
1.1 x t
SRC
V
IL
SR0
, SR1 input voltage
low
V
SS
-0.3 0.3 V
V
IH
SR0
, SR1 input voltage
high
0.85 5.5 V
I
LI
SR0, SR1 input leakage
current
-0.1 0.1 µA
Input glitch immunity
(5)
5. Input glitch immunity is equal to t
SRC
, when both inputs (SR0 and SR1) are low. Otherwise infinite.
SR0 and SR1 asserted t
SRC
s
Test mode
V
TEST
Test mode entry voltage V
CC
+0.9 V
CC
+1.1 V
CC
+1.4 V
t
SRC-INI
Initial test mode time 28 42 56 ms
t
SRC-
SHORT
Shorten Smart Reset™
delay
16.8 21 25.2 ms
