CY22180FSXI

CY22180
Very Low Jitter Field and Factory Programmable
Clock Generator
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 001-15577 Rev. *A Revised January 13, 2009
Features
Low period and cycle-to-cycle jitter
Typical pk-pk period jitter: 60 ps
Wide output frequency range
Commercial temperature: 20–200 MHz
Industrial temperature: 20–166 MHz
Input frequency range
External crystal: 10–30 MHz fundamental crystal
External reference: 10–133 MHz clock
Integrated phase-locked loop (PLL)
Field programmable and factory programmed options
Programmable crystal load capacitor tuning array
3.3V operation
Commercial and industrial temperature ranges
Power down or output enable function
Benefits
Internal PLL generates up to 200 MHz output. Can generate
custom frequencies from an external crystal or a driven source.
In-house programming of samples and prototype quantities
can be done using the CY3672-USB programmer and CY3619
socket adapter. Production quantities are available through
Cypress’s value added distribution partners or by using third
party programmers from BP Microsystems, HiLo Systems, and
others.
Eliminates the need for expensive and difficult to use
higher-order crystals.
Enables fine-tuning of output clock frequency by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
Application compatibility in standard and low-power systems
Enables low-power state or output clocks to High-Z state
PLL
PROGRAMMABLE
CONFIGURATION
OUTPUT
DIVIDER
1
8
3
2 4
5
6
VDD VSS
CLKOUT
REFOUT
XOUT
XIN/CLKIN
PD# or OE
C
XOUT
CXIN
Logic Block Diagram
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CY22180
Document #: 001-15577 Rev. *A Page 2 of 9
Pinouts
Figure 1. CY22180 - 8-Pin SOIC
General Description
The CY22180 is a low jitter clock generator for use in networking,
telecommunication, datacom, consumer electronics, and other
general purpose applications. The CY22180 offers a single
programmable output and an optional copy of the input
frequency. The on-chip reference oscillator is designed to run off
a 10–30 MHz crystal, or a 10–133 MHz external clock signal. The
output frequency range is 20–200 MHz. The CY22180 comes in
an 8-pin SOIC, and requires a 3.3V power supply.
Programming Description
Field Programmable (CY22180FSXC and
CY22180FSXI)
The CY22180 is programmed at the package level, that is, in a
programmer socket. The CY22180 is flash technology based, so
the parts can be reprogrammed up to 100 times. This enables
fast and easy design changes and product updates, and elimi-
nates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer with the CY3619 socket adapter.
CyberClocks Online Software
CyberClocks Online Software is a web-based software appli-
cation that allows the user to custom-configure the CY22180. All
the parameters in Table 1 on page 3 given as “Enter Data” can
be programmed into the CY22180. CyberClocks Online outputs
an industry-standard JEDEC file used for programming the
CY22180. CyberClocks Online is available at
www.cyberclocksonline.com through user registration. For more
information on the registration process refer to the CY3672 data
sheet.
CY3672-USB Programming Kit and CY3619 Socket
Adapter
The Cypress CY3672 FTG programmer and CY3619 socket
adapter are needed to program the CY22180. The socket
adapter comes with small prototype quantities of CY22180. The
CY3619 can be ordered separately, so existing users of the
CY3672-USB programmer need order only the socket adapters
to program the CY22180.
Pin Definitions
Pin Name Description
1 XIN/CLKIN Crystal input or reference clock input.
2 VDD 3.3V power supply.
3 PD#/OE Power down pin, active LOW. If PD# = 0, the PLL and oscillator are powered down and
outputs are weakly pulled low.
Output enable pin, active HIGH. If OE = 1, CLKOUT and REFOUT are enabled. User has
the option of choosing either PD# or OE function.
4 VSS Power supply ground.
5 REFOUT Buffered reference output.
6 CLKOUT Low jitter clock output.
7 NC No connect. Leave this pin floating.
8 XOUT Crystal output. Leave this pin floating if external clock is used.
4
8XIN/CLKIN
6
7
REFOUT
CLKOUT
XOUT1
2
3
VDD
PD#/OE
VSS
NC
5
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CY22180
Document #: 001-15577 Rev. *A Page 3 of 9
Factory Programmed CY22180
Factory programming is available for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. Once
the request has been processed, you receive a new part number
(dash number) and samples with the programmed values. This
part number is used for additional sample requests and
production orders.
Additional information on the CY22180 can be obtained from the
Cypress website at www.cypress.com.
Product Functions
Input Frequency (XIN, pin 1 and XOUT,
pin 8)
The input to the CY22180 can be a crystal or a clock. The input
frequency range for crystals is 10 to 30 MHz, and for clock
signals is 10 to 133 MHz.
C
XIN
and C
XOUT
(pin 1 and pin 8)
The internal load capacitors at pin 1 (C
XIN
) and pin 8 (C
XOUT
)
can be programmed from 12 pF to 60 pF in 0.5 pF increments.
Thus, these programmable capacitors support crystals with C
L
values between 6 pF and 30 pF. The crystal C
L
value, minus
board parasitic capacitance, is the value entered into Cyber-
Clocks Online Software.
If using a driven reference, CyberClocks Online Software sets
C
XIN
and
C
XOUT
to the minimum value 12 pF.
Output Clock (CLKOUT, pin 6)
The output clock can be programmed to any frequency in the
range of 20–200 MHz.
Reference Output (REFOUT, pin 5)
The reference clock output has the same frequency as the input
clock. This output can be programmed to be enabled (clock on)
or disabled (High-Z, clock off) through CyberClocks Online
software. If this output is not needed, Cypress recommends that
users request the disabled (High-Z, Clock Off) option.
Power Down or Output Enable (PD# or OE, pin 3)
The CY22180 can be programmed to include either PD# or OE
function. PD# function can be used to power down the oscillator
and PLL. The OE function disables the outputs but does not turn
off the PLL. PD# achieves lower power consumption, but PLL
start up time means that turn-on time is slower than for OE.
Table 1. Pin Function
Pin Function Input Frequency
Total Xtal Load
Capacitance
Output Frequency
Reference
Output
Power down or Output
Enable
Pin Name XIN and XOUT XIN and XOUT CLKOUT REFOUT PD#/OE
Pin# 1 and 8 1 and 8 6 5 3
Unit MHz pF MHz On or Off Select PD# or OE
Program Value ENTER DATA ENTER DATA ENTER DATA ENTER DATA ENTER DATA
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CY22180FSXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL Lo Jitter Clock Gen 10MHz-133MHz
Lifecycle:
New from this manufacturer.
Delivery:
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