CY22180FSXCT

CY22180
Document #: 001-15577 Rev. *A Page 4 of 9
Absolute Maximum Ratings
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage ......................................–0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing) .... –55°C to +125°C
Junction Temperature................................ –40°C to +125°C
Data Retention at Tj = 125°C ................................> 10 years
Package Power Dissipation......................................350 mW
Static Discharge Voltage.......................................... >
2000V
(per MIL-STD-883, Method 3015) l
Note
1. Guaranteed by characterization, not 100% tested.
Recommended Crystal Specifications
Parameter Description Comments Min Typ. Max Unit
F
NOM
Nominal Crystal Frequency Parallel resonance, fundamental mode,
AT cut
10 30 MHz
C
LNOM
Nominal Load Capacitance 6 30 pF
R
1
Equivalent Series Resistance (ESR) Fundamental mode 25 Ω
DL Crystal Drive Level No external series resistor assumed 0.5 2 mW
Operating Conditions
Parameter Description Min Typ. Max Unit
V
DD
Supply Voltage 3.13 3.30 3.45 V
T
A
Ambient Commercial Temperature 0 70 °C
Ambient Industrial Temperature –40 85 °C
C
LOAD
Max. Load Capacitance at pin 5 and pin 6 10 pF
F
XIN
External Reference Crystal 10 30 MHz
F
CLKIN
External Reference Clock 10 133 MHz
F
CLKOUT
CLKOUT frequency, Commercial Temperature 20 200 MHz
CLKOUT frequency, Industrial Temperature 20 166 MHz
F
REFOUT
REFOUT frequency 10 133 MHz
T
PU
Power up time for all V
DD
s to reach minimum specified voltage (power ramp must
be monotonic)
0.05 500 ms
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5V, V
DD
= 3.3V (source) 10 12 mA
I
OL
Output Low Current V
OL
= 0.5V, V
DD
= 3.3V (sink) 10 12 mA
V
IH
Input High Voltage CMOS levels, 70% of V
DD
0.7V
DD
–V
DD
+ 0.3 V
V
IL
Input Low Voltage CMOS levels, 30% of V
DD
–0.3 0.3V
DD
V
I
IH
Input High Current, PD#/OE V
IN
= V
DD
––10μA
I
IL
Input Low Current, PD#/OE V
IN
= V
SS
, pull up disabled 10 μA
V
IN
= V
SS
, pull up enabled 55 μA
I
OZ
Output Leakage Current Three-state output, PD#/OE = 0 –10 10 μA
C
XIN
or C
XOUT
[1]
Programmable Capacitance
at pin 1 and pin 8
Capacitance at minimum setting 12 pF
Capacitance at maximum setting 60 pF
C
IN
[1]
Input Capacitance at PD#/OE 5 7 pF
I
DD
Supply Current f
IN
= 10 MHz, f
OUT
= 33 MHz, REFOUT off 11 15 mA
I
DDS
Standby current Device powered down with PD# = 0V (driven
reference pulled down)
–1040μA
[+] Feedback
CY22180
Document #: 001-15577 Rev. *A Page 5 of 9
Notes
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, temperature, and output load.
For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions”.
3. Cycle-to-Cycle Jitter (peak) is always less than Period Jitter (peak-to-peak). Peak-to-Peak Period Jitter is the difference between the shortest and longest measured
periods.
AC Electrical Characteristics
[1]
Parameter Description Condition Min Typ Max Unit
DC Output Duty Cycle CLKOUT <
125 MHz, Measured at V
DD
/2 45 50 55 %
Output Duty Cycle CLKOUT > 125 MHz, Measured at V
DD
/2 40 50 60 %
Output Duty Cycle REFOUT, Measured at V
DD
/2
Duty Cycle of CLKIN = 50%
45 50 55 %
SR1 Rising Edge Slew Rate CLKOUT from 20 to 200 MHz;
REFOUT from 10 to 133 MHz. 20%–80% of V
DD
23 V/ns
SR2 Falling Edge Slew Rate CLKOUT from 20 to 200 MHz;
REFOUT from 10 to 133 MHz. 80%–20% of V
DD
23 V/ns
T
PJ1
[2, 3]
CLKOUT pk-pk Period Jitter,
REFOUT off
CLKOUT = 20–200 MHz 75
(±38)
ps
T
PJ2
[2, 3]
CLKOUT pk-pk Period Jitter,
REFOUT off, specific
frequencies
CLKIN = 10 MHz, CLKOUT = 20, 33, 66, 80, 106.25,
125, 133, or 200 MHz
––60
(±30)
ps
CLKIN = 25 MHz, CLKOUT = 125 MHz 56
(±28)
ps
CLKIN = 30 MHz, CLKOUT = 33, 66, 80, 106.25,
125, or 133 MHz
––62
(±31)
ps
CLKIN = 66 MHz, CLKOUT = 33 or 66 MHz 47
(±24)
ps
CLKIN = 66 MHz, CLKOUT = 80, 106.25, 125, 133,
166, or 200 MHz
––68
(±34)
ps
CLKIN = 133 MHz, CLKOUT = 33, 66, or 80 MHz 68
(±34)
ps
CLKIN = 133 MHz,
CLKOUT = 125, 133, or 166 MHz
––52
(±26)
ps
T
PJ3
[2, 3]
CLKOUT pk-pk Period Jitter,
REFOUT on
CLKOUT = 20–200 MHz 150
(±75)
–ps
T
PJ4
[2, 3]
REFOUT pk-pk Period Jitter REFOUT = 10-133 MHz 265
(±133)
ps
t
STP
Power Down Time
(pin 3 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
150 350 ns
T
OE1
Output Disable Time
(pin 3 = OE)
Time from falling edge on OE to stopped outputs
(Asynchronous)
150 350 ns
T
OE2
Output Enable Time
(pin 3 = OE)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
150 350 ns
t
PU1
Power Up Time,
Crystal is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–3.5 5ms
t
PU2
Power Up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous), reference clock at
correct frequency
–2 3ms
[+] Feedback
CY22180
Document #: 001-15577 Rev. *A Page 6 of 9
Notes
4. Since the load capacitors (C
XIN
and C
XOUT
) are provided by the CY22180, no external capacitors are needed on the XIN
and XOUT pins to match the crystal
load capacitor (C
L
). Only a single 0.1-μF bypass capacitor is required on the V
DD
pin.
5. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
Figure 2. Application Circuits
[4, 5]
Switching Waveforms
Figure 3. Duty Cycle Timing (DC = t
1A
/t
1B
)
Figure 4. Output Rise/Fall Time (CLKOUT and REFOUT)
0.1uF
1
3
2
4
5
6
7
8
XIN/CLKIN
VDD
PD#/OE
VSS
REFOUT
CLKOUT
NC
XOUT
Power
CY22180
CLKIN
no
connect
no
connect
VDD or
control
t
1A
t
1B
OUTPUT
OUTPUT
Tr
V
DD
0V
Tf
Output Rise time (Tr) = (0.6 x V
DD
)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x V
DD
)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
[+] Feedback

CY22180FSXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN PROG 8-SOIC
Lifecycle:
New from this manufacturer.
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