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MIC2593-2YTQ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Micrel, Inc. MIC2593
September 2008
16
M9999-092208
Register Set and Programmer’s Model
Target Register
Common
Byte Value
Label Description Read Write
Power-On
Default
RESERVED Do not Use 00
h
n/a n/a
RESERVED Do not Use 01
h
n/a n/a
CNTRLA Control Register Slot A 02
h
02
h
00
h
CNTRLB Control Register Slot B 03
h
03
h
00
h
STATA Slot A Status 04
h
04
h
00
h
STATB Slot B Status 05
h
05
h
00
h
CS Common Status Register 06
h
06
h
Xxxx 0000
b
RESERVED Reserved / Do not Use 07
h
0FF
h
07
h
0FF
h
Undifined
Table 4. MIC2593 Register Addresses
S1001 0A000000XXA AP
MIC2593 Slave Address
DATA
CLK
Command Byte to MIC2593
Data Byte to MIC2593
START STOP
R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE
Master to slave transfer,
i.e., DATA driven by master.
Slave to master transfer,
i.e., DATA driven by slave.
Figure 9.WRITE_BYTE Protocol
S 1 0 0 1 A2A1A0 A2A1A00A000000XXAS1 1 100 A /A P
MIC2593 Slave Address
DATA
CLK
Command Byte to MIC259
MIC2593 Slave Address Data Read From MIC2593
START START STOP
R/W = WRITE R/W = READACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE NOT ACKNOWLEDGE
Master to slave transfer,
i.e., DATA driven by master.
Slave to master transfer,
i.e., DATA driven by slave.
Figure 10.READ_BYTE Protocol
S1001 1A /A P
MIC2593 Slave Address
DATA
CLK
Byte Read from MIC2593
START STOP
R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE
Master to slave transfer,
i.e., DATA driven by master.
Slave to master transfer,
i.e., DATA driven by slave.
Figure 11.RECEIVE_BYTE Protocol
Micrel, Inc. MIC2593
September 2008
17
M9999-092208
Detailed Register Descriptions below:
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
Control Register, Slot A (CNTRLA)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read-only read-only read-only read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved Reserved MAINA AUXA
Bit(s) Function Operation
AUXAPG AUX output power-good status, Slot A
1 = Power-is-Good
(VAUXA Output is above its UVLO threshold)
MAINAPG MAIN output power-good status, Slot A
1 = Power-is-Good
(MAINA Outputs are above their UVLO thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
D[2] Reserved Always read as zero
MAINA MAIN enable control, Slot A 0 = Off, 1 = On
AUXA VAUX enable control, Slot A 0 = Off, 1 = On
Power-Up Default Value: 0000 0000
b
= 00
h
Read Command_Byte Value (R/W): 0000 0010
b
= 02
h
The power-up default value is 00
h
. Slot is disabled upon power-up, i.e., all supply outputs are off.
Control Register, Slot A (CNTRLB)
8-Bits, Read/Write
Control Register, Slot B (CNTRLB)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read-only read-only read-only read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved Reserved MAINB AUXB
Bit(s) Function Operation
AUXBPG AUX output power-good status, Slot B
1 = Power-is-Good
(VAUXB Output is above its UVLO threshold)
MAINBPG MAIN output power-good status, Slot B
1 = Power-is-Good
(MAINB Outputs are above their UVLO thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
D[2] Reserved Always read as zero
MAINB MAIN enable control, Slot B 0 = Off, 1 = On
AUXB VAUX enable control, Slot B 0 = Off, 1 = On
Power-Up Default Value: 0000 0000
b
= 00
h
Command_Byte Value (R/W): 0000 0011
b
= 03
h
The power-up default value is 00
h
. Slot is disabled upon power-up, i.e., all supply outputs are off.
Micrel, Inc. MIC2593
September 2008
18
M9999-092208
Status Register, Slot A (STATA)
8-Bits, Read-Only
Status Register, Slot A (STATA)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read/write read/write read/write read/write
FAULTA MAINA VAUXA VAUXAF 12MVAF 12VAF 5VAF 3VAF
Bit(s) Function Operation
FAULTA FAULT Status, Slot A
1 = /FAULTA pin asserted
(/FAULTA pin is LOW)
0 = /FAULTA pin de-asserted
(/FAULTA pin is HIGH)
See Notes 1 and 2
MAINA MAIN Enable Status, Slot A
Represents the actual state (on/off) of the four Main
Power outputs for Slot A (+12V, –12V, +5V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
VAUXA VAUX Enable Status, Slot A
Represents the actual state (on/off) of the Auxiliary
Power output for Slot A
1 = AUX Power ON
0 = Main Power OFF
VAUXAF Overcurrent Fault: VAUXA supply A 1 = Fault, 0 = No fault
12MVAF Overcurrent Fault: –12V supply A 1 = Fault, 0 = No fault
12VAF Overcurrent Fault: +12V supply A 1 = Fault, 0 = No fault
5VAF Overcurrent Fault: 5V supply A 1 = Fault, 0 = No fault
3VAF Overcurrent Fault: 3V supply A 1 = Fault, 0 = No fault
Power-Up Default Value: 0000 0000
b
= 00
h
Command_Byte Value (R/W): 0000 0100
b
= 04
h
The power-up default value is 00
h
. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to
anovercurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and de-assert /INT.
Thestatus of the /FAULTA pin is not affected by reading the Status Register or by clearing active status bits.
Note 1. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA.
If FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to
reset FAULTA.
Note 2. Neither the FAULTA bit nor the /FAULTA pin is active when the MIC2593 power paths are controlled by the System Management
Interface. When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

MIC2593-2YTQ

Mfr. #:
Buy MIC2593-2YTQ
Manufacturer:
Microchip Technology / Micrel
Description:
Hot Swap Voltage Controllers Dual-slot PCI Hot Swap Power Controller w/o IPMI support
Lifecycle:
New from this manufacturer.
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