Micrel, Inc. MIC2593
September 2008
10
M9999-092208
Test Circuit
t
1
SCL
SDA
Data In
SDA
Data Out
t
4
t
2
t
3
t
5
Figure 1. SMBus Timing
6V
12VGATE
V
THFAST
V
THILIMIT
t
OFF(12V)
1V
3VGATE
V
THFAST
V
THLIMIT
t
OFF3
Figure 2. 12V Current Limit Response Timing Figure 3. 3V Current Limit Response Timing
0 Amps
I
OUT(AUX)
I
OUT(AUX)
I
LIM(AUX)
Must Trip
May Not Trip
I
AUX(THRESH)
0 Amps
I
OUT(AUX)
t
SC(TRAN)
I
LIM(AUX)
I
SC(TRAN)
Figure 4. VAUX Current Limit Threshold Figure 5. VAUX Current Limit Response Timing
Micrel, Inc. MIC2593
September 2008
11
M9999-092208
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying
live supply voltages (“hot-plugged”), high inrush currents
often result due to the charging of bulk capacitance that
resides across the circuit board’s supply pins. This
transient inrush current can cause the system’s supply
voltages to temporarily go out of regulation, causing data
loss or system lock-up. In more extreme cases, the
transients occurring during a hot plug event may cause
permanent damage to connectors or on-board
components.
The MIC2593 addresses these issues by limiting the
inrush currents to the load (PCI Board), and thereby
controlling the rate at which the load’s circuits turn-on. In
addition to this inrush current control, the MIC2593 offers
input and output voltage supervisory functions and current
limiting to provide robust protection for both the system
and circuit board.
System Interfaces
The MIC2593 employs two system interfaces: the
hardware Hot Plug Interface (HPI) and the System
Management Interface (SMI). The HPI includes ON[A/B],
AUXEN[A/B], as well as /FAULT[A/B]; the SMI consists of
SDA, SCL, and /INT, whose signals conform to the levels
and timing of the SMBus specification. The MIC2593 can
be operated exclusively from the SMI, or can employ the
HPl for power control while continuing to use the SMI for
access to all but the power control registers.
In addition to the basic power control features of the
MIC2593 accessible by the HPI, the SMI also gives the
host access to the following information from the part:
1. Fault conditions occurring on each supply.
2. GPI[A/B] pin status.
When using the System Management Interface for power
control, do not use the Hot Plug Interface. Conversely,
when using the Hot Plug Interface for power control, do
not execute power control commands over the System
Management Interface bus (all other register accesses via
the SMI bus remain permissible while in the HPI control
mode). When utilizing the SMI exclusively, the HPI input
pins ON[A/B] and AUXEN[A/B] should be tied to ground
as shown below in Figure 6 (Disabling HPI when SMI
control is used). This configuration safeguards the power
slots in the event that the SMBus communication link is
disconnected for any reason.
Additionally, when utilizing the HPI exclusively, the
SMBus (or SMI) will be inactive if the input pins (SDA,
SCL, A0, A1, and A2) are configured as shown in Figure 6
below (disabling SMI when HPI Control is used).
Power-On Reset and Power Cycling
The MIC2593 utilizes VSTBY[A/B] as the main supply
input source. VTSBY[A/B] is required for proper operation
of the MIC2593 SMBus interface and registers and must
be applied at all times. A Power-On Reset (POR) cycle is
initiated after VSTBY[A/B] rises above its UVLO threshold
and remains valid at that voltage for 500µs. All internal
registers are cleared after POR. If VSTBY[A/B] is
recycled, the MIC2593 enters a new power-on reset
cycle. VSTBY[A/B] must be the first supply input applied
followed by the MAIN supply inputs of 12V
IN
, 12MV
IN
,
5V
IN
, and 3V
IN
. The MAIN supply inputs may be applied in
any order. The SMBus is ready for access at the end of
the POR interval (500µs after VSTBY[A/B] is valid). All
outputs remain off during t
POR
.
MIC2593
A2
/INT
SDA
SCL
A0
V
STBY
A1
100k
47
48
37
39
40
41
100k
Disabling SMI when
HPI Control is used
Disabling HPI when
SMI Control is used
100k
/INT
AUXENA
AUXENB
ONA
ONB
MIC2593
45
42
44
43
Figure 6. Input Pin Configuration for
Disabling HPI/SMI Control
Micrel, Inc. MIC2593
September 2008
12
M9999-092208
Power-Up Cycle
When a slot is off, the 5VGATE and 3VGATE pins are
held low with an internal pull-down current source. When
a slot’s MAIN outputs are enabled by applying a rising-
edge signal at the ON[A/B] control input and all input
voltages are above their respective undervoltage lockout
thresholds, all four main supplies will then execute a
controlled turn on. The 5VGATE and 3VGATE pins are
each connected to a constant current source of 25µA,
nominal. Both the 5V and 3.3V outputs act as source
followers, where:
[
]
TH(ON)GATESOURCE
VVV =
until the associated output is equal to its input. The
voltages on the gates of the external MOSFETs for the 5V
and 3.3V MAIN supplies will continue to rise to
approximately 11.5V, ensuring minimum R
DS(ON)
of the
MOSFET. Note that a delay exists between the ON
command to a slot and the appearance of voltage at the
slot’s 3.3V or 5V MAIN output. This delay is the time
required to charge the 3V or 5V GATE output up to the
threshold voltage of the external MOSFET (typically about
4V). For the 5V and 3.3V MAIN supplies, the source
(output) side of the external MOSFET will reach the drain
(input) voltage in a time given by:
()
E)GATE(SOURC
DRAINGATE
DELAY
I
VC
t
×
=
Table 1 provides a reference list of the expected GATE
output slew rate for the 3.3V and 5V supplies using
several (decade-scale) standard capacitors.
I
SLEW
= 25µA
C
GATE
dv/dt (load)
0.001µF 25000V/s
0.01µF 2500V/s
0.1µF 250V/s
1µF 25V/s
Table 1. 3.3V/5V Output Slew Rate Selection
For the +12V and –12V supplies, the output slew rate is
controlled by capacitors connected to the 12VSLEWA and
12VSLEWB pins. To determine the minimum value of the
slew rate capacitor, (C
SLEW
), and to ensure the device
does not enter into current limit during start-up, the
following equation is used:
LOAD
MV]LIM[12V/12
SLEW
SLEW
C
I
I
(min)C ×=
where C
LOAD
is the load capacitance connected to the
+12V and –12V outputs, I
LIM[12V/12MV]
are the current limit
slow-trip thresholds and I
SLEW
is the slew rate charge
current found in the “Electrical Characteristics” table. The
slew rate dv/dt is computed by:
6
SLEW
SLEW
10C
I
load) (at dv/dt
×
=
By appropriately selecting the value of C
SLEW
, the
magnitude of the inrush current will not exceed the current
limit for a given load capacitance. Since one capacitor
fixes the slew rate for both +12V and –12V, the capacitor
value should be chosen to provide the slower slew rate of
the two. Table 2 depicts the ±12V output slew rate for
various values of C
SLEW
.
I
SLEW
= 22µA
C
GATE
dv/dt (load)
0.001µF 22V/ms
0.01µF 2.2V/ms
0.1µF 0.22V/ms
1µF 0.022V/ms
Table 2. ±12V Output Slew Rate Selection
Power Down Cycle
When a slot is turned off, internal switches are connected
to each of the outputs to discharge the PCI board's
bypass capacitors to ground.
Standby Mode
Standby mode is entered when any (one or more)
enabled MAIN supply input (12V
IN
, 12MV
IN
, 5V
IN
and/or
3V
IN
) drops below its respective UVLO threshold. The
MIC2593 supplies two 3.3V auxiliary outputs, VAUX[A/B],
satisfying PCI 2.x specifications. These outputs are fed
via the VSTBY[A/B] input and controlled by the
AUXEN[A/B] inputs or via their SMI bus Control Registers.
These outputs are independent of the MAIN outputs:
should one or more of the MAIN supply inputs move
below its UVLO thresholds, VAUX[A/B] will still function as
long as VSTBY[A/B] is present. Prior to entering standby
mode, ONA and ONB (or the MAINA and MAINB bits in
the Control Registers) inputs should be de-asserted. If this
is not done, the MIC2593 will assert /FAULT and also
/INT if interrupts are enabled, when the MIC2593 detects
an undervoltage condition on a supply input.
Circuit Breaker Functions
The MIC2593 provides an electronic circuit breaker
function that protects against excessive loads, such as
short circuits, at each supply. When the current from one
or more of a slot’s MAIN outputs exceeds the current limit
threshold (50mV/R
SENSE
for 3.3V and 5V, 1.0A for +12V,
and/or 0.2A for –12V) for a duration greater than the
overcurrent timer, t
FLT
, the circuit breaker is tripped and all
MAIN supplies (all outputs except VAUX[A/B]) are shut
off. Should the load current exceed I
THFAST
(+12V and –
12V), or cause a MAIN output’s V
SENSE
to exceed V
THFAST
(+3.3V and +5V), the outputs are shut off with no delay.
Undervoltage conditions on the MAIN supply inputs also

MIC2593-2BTQ

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IC CTRLR HOTPLUG PCI DUAL 48TQFP
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