LTC3788
22
3788fc
applicaTions inForMaTion
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2.
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTV
CC
DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC3788 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continue to be regulated. More cycles will be skipped when
V
IN
increases. Once V
IN
rises above V
OUT
, the loop works
to keep the top MOSFET on continuously. The minimum
on-time for the LTC3788 is approximately 110ns.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency can
be expressed as:
%
Efficiency = 100% – (L1 + L2 + L3 + ...)
where
L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3788 circuits: 1) IC V
IN
current, 2) INTV
CC
regulator current, 3) I
2
R losses, 4) Bottom MOSFET
transition losses.
1. The V
IN
current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. V
IN
current typically results
in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOS-
FETs. Each time a MOSFET gate is switched from low to
high to low again, a packet of charge, dQ, moves from
INTV
CC
to ground. The resulting dQ/dt is a current out
of INTV
CC
that is typically much larger than the control
circuit current. In continuous mode, I
GATECHG
= f(Q
T
+
Q
B
), where Q
T
and Q
B
are the gate charges of the topside
and bottom side MOSFETs.
3. DC I
2
R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC
board traces
and cause the efficiency to drop at high output currents.
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low
input voltages. Transition losses can be estimated from:
Transition Loss = (1.7)
V
OUT
3
V
IN
I
O(MAX)
C
RSS
f
Other hidden losses, such as copper trace and internal
battery resistances, can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system-level losses during the
design phase.
Figure 6. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3788 F06
400
200
500
700
900
300
100
0
65 75 85 95 105 115
125
LTC3788
23
3788fc
applicaTions inForMaTion
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal toI
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge
or discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recov-
ery time V
OUT
can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen
at this pin. The bandwidth can also be
estimated
by examining the rise time at the pin. The I
TH
external components shown in the Figure 9 circuit will
provide an adequate starting point for most applications.
The I
TH
series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is complete
and the particular output capacitor type and value have
been determined. The output capacitors must be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time ofs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so
this
signal cannot
be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing R
C
and the bandwidth of the loop will be increased by de-
creasing C
C
. If R
C
is increased by the same factor that C
C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • C
LOAD
. Thus, a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume V
IN
=
12V(nominal), V
IN
= 22V (max), V
OUT
= 24V, I
OUT(MAX)
=
4A, V
SENSE(MAX)
= 75mV, and f = 350kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
I
L
=
V
IN
f L
1
V
IN
V
OUT
A 6.8µH inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
LTC3788
24
3788fc
applicaTions inForMaTion
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R
SENSE
75mV
9.25A
= 0.008
Choosing 1% resistors: R
A
= 5k and R
B
= 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET can
be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: R
DS(ON)
= 0.012Ω, C
MILLER
= 150pF.
At maximum input voltage with T(estimated) = 50°C:
P
MAIN
=
(24V 12V) 24V
(12V)
2
(4A)
2
1+(0.005)(50°C 25°C)
[ ]
0.008
+ (1.7)(24V)
3
4A
12V
(150pF)(350kHz) = 0.7W
C
OUT
is chosen to filter the square current in the output.
The maximum output current peak is:
I
OUT(PEAK)
= 4 1+
31%
2
= 4.62A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 23.1mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 7. Figure 8 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with C
OUT
.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
INTVCC
must return to the combined C
OUT
(–) terminals.
The path formed by the bottom N-channel MOSFET and
the C
IN
capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to
each other.
3. Do the LTC3788 VFB pins’ resistive dividers connect to
the (+) terminals
of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
4. Are the SENSE
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE
+
and SENSE
should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTV
CC
decoupling capacitor connected close
to the IC, between the INTV
CC
and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additionalF ceramic capacitor placed
immediately next to the INTV
CC
and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3788 and occupy a minimal
PC trace area
.
7. Use a modifiedstar ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.

LTC3788IUH#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2-Phase, 2x Out Sync Boost Cntr
Lifecycle:
New from this manufacturer.
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