MC100EPT24DTG

© Semiconductor Components Industries, LLC, 2016
August, 2016 Rev. 10
1 Publication Order Number:
MC100EPT24/D
MC100EPT24
3.3V LVTTL/LVCMOS to
Differential LVECL Translator
Description
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a 3.3 V, +3.3 V and ground are required. The small outline
8-lead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
Features
350 ps Typical Propagation Delay
Maximum Input Clock Frequency = > 1.0 GHz Typical
The 100 Series Contains Temperature Compensation
Operating Range:
V
CC
= 3.0 V to 3.6 V; V
EE
= 3.6 V to 3.0 V; GND = 0 V
PNP LVTTL Input for Minimal Loading
Q Output will Default HIGH with Input Open
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
MC100EPT24DG SOIC8 NB
(Pb-Free)
98 Units / Tube
MC100EPT24DR2G
2500 Tape & Reel
TSSOP8
(Pb-Free)
MC100EPT24MNR4G 1000 Tape & Reel
MC100EPT24DTG 100 Units / Tube
SOIC8 NB
(Pb-Free)
DFN8
(Pb-Free)
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
SOIC8 NB
D SUFFIX
CASE 75107
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R02
ALYWG
G
KA24
1
8
1
8
1
8
KPT24
ALYW
G
1
8
3U MG
G
14
SOIC8 NB TSSOP8 DFN8
DFN8
MN SUFFIX
CASE 506AA
MC100EPT24
www.onsemi.com
2
1
2
3
45
6
7
8
Q
GND
V
CC
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
D
Q
NC
NC
V
EE
LVTTL
LVECL
Table 1. PIN DESCRIPTION
PIN
Q, Q
D LVTTL Input
FUNCTION
Differential LVECL Outputs
V
CC
GND Ground
Positive Supply
V
EE
Negative Supply
NC No Connect
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient ther-
mal conduit. Electrically connect to the
most negative supply (GND) or leave
unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor N/A
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8 NB
TSSOP8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 181 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EPT24
www.onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V V
EE
= 3.3V 3.8 V
V
EE
Negative Power Supply GND = 0 V V
CC
= 3.3V 3.8 V
V
IN
Input Voltage GND = 0 V V
I
V
CC
0 to V
CC
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
50 lfpm
SOIC8 NB
SOIC8 NB
190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC8 NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
50 lfpm
TSSOP8
TSSOP8
185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
50 lfpm
DFN8
DFN8
129
84
°C/W
T
sol
Wave Solder (Pb-Free) 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
Table 4. LVTTL INPUT DC CHARACTERISTICS (V
CC
= 3.3 V, V
EE
= 3.6 V to 3.0 V, GND = 0.0 V; T
A
= 40°C to 85°C)
Symbol Characteristic Condition Min Typ Max Unit
I
IH
Input HIGH Current V
IN
= 2.7 V 20
mA
I
IHH
Input HIGH Current HIGH Voltage V
CC
= V
IN
= 3.8 V 100
mA
I
IL
Input LOW Current V
IN
= 0.5 V 0.6 mA
V
IK
Input Clamp Voltage I
IN
= 18 mA 1.0 V
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 50 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. NECL OUTPUT DC CHARACTERISTICS (V
CC
= 3.3 V, V
EE
= 3.3 V, GND = 0.0 V (Note 1))
Symbol
Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
V
OH
Output HIGH Voltage (Note 2) -1145 1020 -895 -1145 1020 -895 -1145 1030 -895 mV
V
OL
Output LOW Voltage (Note 2) -1945 1820 -1695 -1945 1820 -1695 -1945 1820 -1695 mV
I
CC
Positive Power Supply Current 2.0 4.0 2.0 4.0 2.0 4.0 mA
I
EE
Negative Power Supply Current 20 30 38 20 30 38 20 30 38 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 50 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Output levels will vary 1:1 with GND. V
EE
can vary ± 0.3 V.
2. Outputs are terminated through a 50 W resistor to GND 2V.

MC100EPT24DTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 3.3V LVTTL/LVCMOS to Diff LVECL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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