MC100EPT24DR2

MC100EPT24
www.onsemi.com
4
Table 6. AC CHARACTERISTICS (V
CC
= 0 V; V
EE
= 3.0 V to 5.5 V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 1))
Symbol
Characteristic
40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Input Clock Frequency
(Figure 2)
> 1 > 1 > 1 GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential (Note 2)
300 500 800 300 530 800 300 560 800 ps
t
JITTER
RMS Random Clock Jitter (Figure 2) 0.2 < 1 0.2 < 1 0.2 < 1 ps
t
r
t
f
Output Rise/Fall Times Q, Q
(20% 80%) @ 50 MHz
70 125 170 80 130 180 100 150 200 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 50 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 W to GND 2.0 V.
2. Specifications for standard TTL input signal.
0
100
200
300
400
500
600
700
800
900
100 300 500 700 900 1100 1300
1
2
3
4
5
6
7
8
9
Figure 2. Output Voltage Amplitude (V
OUTpp
)/RMS Jitter
vs. Input Clock Frequency at Ambient Temperature
INPUT CLOCK FREQUENCY (MHz)
(JITTER)
OUTPUT VOLTAGE AMPLITUDE (mV)
RMS RANDOM CLOCK JITTER (ps)
MC100EPT24
www.onsemi.com
5
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
Termination of ECL Logic Devices)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
2.0 V
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
MC100EPT24
www.onsemi.com
6
PACKAGE DIMENSIONS
SOIC8 NB
D SUFFIX
CASE 75107
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) Z
S
X
S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*

MC100EPT24DR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC TRNSLTR UNIDIRECTIONAL 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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