6.42
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
7
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
(1,3)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
Timing Waveform of Write Cycle No. 3
(BHE, BLE Controlled Timing)
(1,3)
ADDRESS
CS
DATA
IN
6442 drw
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
ADDRESS
CS
DATA
IN
6442 drw 1
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
