LT3973/LT3973-3.3/LT3973-5
12
3973fb
For more information www.linear.com/LT3973
APPLICATIONS INFORMATION
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis
-
tors according to:
R1= R2
OUT
1.21
– 1
Reference designators refer to the Block Diagram. Note
that choosing larger resistors will decrease the quiescent
current of the application circuit.
Setting the Switching Frequency
The LT3973 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2.2MHz
by using a resistor tied from the RT pin to ground. A table
showing the necessary R
T
value for a desired switching
frequency is in Table 1.
Table 1. Switching Frequency vs R
T
Value
SWITCHING FREQUENCY (MHz) R
T
VALUE (kΩ)
0.2
0.3
0.4
0.5
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
732
475
340
267
215
150
115
90.9
73.2
61.9
51.1
43.2
36.5
Operating Frequency Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, and maximum input voltage.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. The disad
-
vantages are
lower efficiency, and narrower input voltage
range
at constant-frequency. The highest acceptable
switching frequency (f
SW(MAX)
) for a given application
can be calculated as follows:
f
SW(MAX)
=
OUT
D
t
ON(MIN)
V
IN
– V
SW
+ V
D
( )
where V
IN
is the typical input voltage, V
OUT
is the output
voltage, V
D
is the integrated catch diode drop (~0.7V),
and V
SW
is the internal switch drop (~0.5V at max load).
This equation shows that slower switching frequency is
necessary to accommodate high V
IN
/V
OUT
ratio. This is
due to the limitation on the LT3973’s minimum on-time.
The minimum on-time is a strong function of temperature.
Use the minimum switch on-time curve (see Typical Per
-
formance Characteristics)
to design for an application’s
maximum temperature, while adding about 30% for
part-to-part variation. The minimum duty cycle that can
be achieved taking this on-time into account is:
DC
MIN
= t
ON(MIN)
• f
SW
where f
SW
is the switching frequency, and the t
ON(MIN)
is
the minimum switch on-time.
A good choice of switching frequency should allow ad
-
equate input voltage range (see next two sections) and
keep the inductor and capacitor values small.
Minimum Input Voltage Range
The minimum input voltage for regulation is determined
by either the LT3973’s minimum operating voltage of
4.2V, its maximum duty cycle, or the enforced minimum
dropout voltage. See the typical performance
character-
istics section for the minimum input voltage across load
for outputs of 3.3V and 5V.
The
duty cycle is the fraction of time that the internal
switch is on during a clock cycle. Unlike many fixed fre
-
quency regulators,
the LT3973 can extend its duty cycle
by remaining on for multiple clock cycles. The LT3973
will not switch off at the end of each clock cycle if there
is sufficient voltage across the boost capacitor (C3 in
the Block Diagram). Eventually, the voltage on the boost
capacitor falls and requires refreshing. When this occurs,
the switch will turn off, allowing the inductor current to
recharge the boost capacitor. This places a limitation on
the maximum duty cycle as follows:
DC
MAX
= 1/(1+1/ β
SW
)
where β
SW
is equal to the SW pin current divided by
the BOOST pin current (see the Typical Performance
Characteristics section), generally leading to a DC
MAX
of
