MAX2371/MAX2373
LNAs with Step Attenuator and VGA
_______________________________________________________________________________________ 9
The MAX2371/MAX2373 can be turned off in transmit or
battery-save standby mode. The receive-enable pin
(RX_EN) also can turn off the devices even if V
CC
is not
removed, because multiple LNAs can be connected to
the same V
CC
for multiband applications.
The devices allow external matching networks to configure
operation in a wide frequency range. Refer to the EV kit
schematic for a guide to designing the matching network.
Applications Information
AGC
The AGC of the MAX2371/MAX2373 is controlled by an
external voltage at pin AGC. The amplifier is at full gain
if the voltage at pin AGC is nominally V
CC
/2. It is at min-
imum gain if the voltage at pin AGC is V
CC
. The AGC
attenuation range, which is continuously variable, is
specified at 45dB. The IP3 will degrade slightly as AGC
reduces the gain.
The devices include two gain modes. Set RF_ATTN high
to enable the low-gain mode, which reduces the gain by
about 20dB. Low-gain mode will increase the system IP3
by approximately 18dB, which provides strong signal
overload and IM protection. An external pin (RF_ATTN)
controls switching between gain modes so this function
can be combined with overall AGC control. AGC is inde-
pendent of the choice of gain mode. The gain step
between modes is in addition to the range of AGC, allow-
ing a large overall gain-control range.
AGC Response
A linear transfer function between the AGC control signal
and the AGC attenuation is realized in dB. The linear
relationship in dB/V is maintained to ±10% over a speci-
fied attenuation range. Any compensation for gain-mode
change must come from the AGC control. After reducing
gain by switching the RF_ATTN pin, reduce the AGC
voltage to achieve the desired overall gain.
The LNA current also can be changed by toggling the
LNA_I pin. This operation is independent of gain mode
and AGC control. The low-current mode is intended as a
second (reduced-current) quiescent point of operation
for strong-signal operating environments.
Matching Networks
For best performance, match LNA_IN and LNA_OUT to
50Ω for the band of operation. Typical matching circuits
for two bands (136MHz to 174MHz and 850MHz to
940MHz) are shown in the EV kit. The chip impedance
changes minimally from low to high gain and with AGC.
The input requires a DC-blocking capacitor. The size of
this capacitor influences the startup time and IP3. There
is a trade-off between these: A large DC-blocking
capacitor means a good IP3 and slow startup. The maxi-
mum startup time is determined by the equation below:
MAXT
START
= 40 ✕ C
AC
✕ R
SET
,
where C
AC
= AC-coupling cap in Farads, R
SET
= current-
setting resistor in Ω.
IP3 will improve with the separation of the interfering
tones, so a wider channel system can use a smaller DC-
blocking capacitor and achieve a better IP3. The cus-
tomer also can change the emitter inductor at LNA_E to
get the desired linearity and gain. Changing this induc-
tor value requires a change to the input match. The out-
put is an open collector and needs a pullup inductor. A
load resistor also can be connected across it. The resis-
tor determines the trade-off between the bandwidth of
the match and the gain. A small load resistor means a
wider match and lower gain.
Layout Issues
For best performance, pay attention to power-supply
issues as well as to the layout of the RFOUT matching
network. The EV kit can be used as a layout example.
Ground connections followed by supply bypass are the
most important.
Power-Supply Bypassing
The MAX2371/MAX2373 have two supply pins:
LNA_V
CC
and RF_V
CC
. These must be bypassed sepa-
rately. It is assumed that there is a large capacitor
decoupling the power supply. LNA_V
CC
and RF_V
CC
are each decoupled with 1500pF (MAX2371) or 100pF
(MAX2373) capacitor. Use separate paths to the ground
plane for each of the bypass capacitors, and minimize
trace length to reduce inductance. The exposed pad
must be connected to system ground with very low
impedance vias.
Power-Supply Layout
To minimize coupling between sections of the IC, the
ideal power-supply layout is a star configuration with a
large decoupling capacitor at a central V
CC
node. The
V
CC
traces branch from this central node, each to a sep-
arate V
CC
node in the PC board. At the end of each
trace is a bypass capacitor that has low ESR at the RF of
operation. This arrangement provides local decoupling
at each V
CC
pin. At high frequencies, any signal leaking
out of one supply pin sees a relatively high impedance
(formed by the V
CC
trace inductance) to the central V
CC
node and an even higher impedance to any other supply
pin, as well as a low impedance to ground through the
bypass capacitor.
