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LT1573CS8-2.5#PBF

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10
LT1573
sn1573 1573fas
Thermal Considerations
The thermal characteristics of several components need
to be considered; the LT1573, the pass transistor and
resistor R
D
. Power dissipation should be calculated based
on the worst-case conditions seen by each component
during normal operation.
1. Power Dissipation of the LT1573: The worst-case
power dissipation in the LT1573 is a function of drive
current, supply voltage and the value of R
D
. Worst-case
dissipation for the LT1573 occurs when the drive cur-
rent is equal to approximately one half of its maximum
value. The worst-case power dissipation in the LT1573
can be calculated by the following formula:
P
VV
R
R
D
IN BE
D
D
=
−
()
>
2
4
minimum R for latch- off function
D
(2)
where,
V
IN
= the maximum input voltage to the circuit
V
BE
= the minimum emitter/base voltage of the PNP
pass transistor
Following the previous design example for selecting
resistor R
D
, the power dissipation of LT1573 is calcu-
lated from Eq (2):
PW
D
=
−
()
()
=
55 065
424
025
2
..
.
For some operating conditions R
D
may be replaced with
a short. This is possible in applications where the
operating requirements (input voltage and drive cur-
rent) are at the low end and the output will not be
shorted. For R
D
= 0, the following formula may be used
to calculate the maximum power dissipation in the
LT1573:
P
D
= (V
IN
– V
BE
)(I
DRIVE
) (3)
where,
V
IN
= the maximum input voltage
V
BE
= the minimum emitter/base voltage of the PNP
I
DRIVE
= the required maximum drive current
2. Power Dissipation of the Resistor R
D
: The worst-case
power dissipation in resistor R
D
needs to be calculated
so that the power rating of the resistor can be deter-
mined. The worst-case power dissipation in this resis-
tor will occur when the drive current is at a maximum.
The power dissipation can be calculated from the fol-
lowing formula:
P
VV V
R
RD
IN BE DRIVE
D
=
−−
()
2
(4)
where,
V
IN
= the maximum input voltage
V
BE
= the minimum emitter/base voltage of the PNP
V
DRIVE
= the voltage at the LT1573 DRIVE pin
= V
SAT
of the DRIVE pin in the worst case
Following the previous design example, the power
dissipation of resistor R
D
is calculated from Eq (4):
PW
RD
=
−−
()
=
55 065 039
24
083
2
.. .
.
3. Power Dissipation of the PNP Transistor: The worst-
case power dissipation in the PNP pass transistor is
simply equal to:
P
PNP
= (V
IN
– V
OUT
)(I
OUT
) (5)
where,
V
IN
= the maximum input voltage
I
OUT
= the maximum output current
Following the previous design example, the power
dissipation of PNP transistor is calculated from Eq (5):
P
PNP
= (5.5 – 3.3)(5) = 11W
The LT1573 series regulators have internal thermal
limiting designed to protect the device during overload
conditions. For continuous normal load conditions,
the maximum junction temperature rating of 125°C
must not be exceeded. It is important to give careful
consideration to all sources of thermal resistance from
junction to ambient. For surface mount devices, heat
sinking is accomplished by using the heat spreading
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LT1573
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capabilities of the PC board and its copper traces. Table
3 lists some typical values for the thermal resistance of
the LT1573. Measured values of thermal resistance for
a specific board size with different copper areas are
listed. All measurements were taken in still air on 3/32
"
FR-4 board with 2oz copper. It is possible to achieve
significantly lower values with thinner multilayer boards.
Compensation
In order to improve the transient response to regulator
output load variation, a capacitor in series with a resistor
can be inserted between the V
OUT
and COMP pins. For the
microprocessor power supply regulator system based on
the LT1573 and the PNP transistor D45H11 with 24 1µF
surface mount ceramic capacitors in parallel with one
220µF surface mount tantalum capacitor at the output as
shown in Figure 1, a 100pF capacitor in series with a 1k
resistor is recommended. In theory, the output capacitor
forms the dominant pole of the regulator system. An
internal compensation capacitor forms another pole. The
external compensation capacitor and resistor form a zero
which adds phase margin to the regulator system to
prevent high frequency oscillation. The LT1573 has an
internal pole at approximately 5kHz. An external compen-
sation zero between 10kHz and 100kHz is usually required
to stabilize the regulator. The zero frequency is primarily
determined by the compensation capacitor and can be
roughly calculated by the following equation:
f kHz
pF
CpF
C
ZERO
COMP
COMP
=
()
()
()
≤≤40
30
10 100,
A compensation resistor between 1k and 10k is sug-
gested. A compensation resistor of 5k works for most
cases. In some cases, a greater compensation resistor is
needed to stop oscillation above 1MHz. In some cases, the
output capacitor may have enough equivalent series resis-
tance (ESR) to generate the required zero and the external
compensation zero may not be needed.
Output Capacitor
The LT1573 is designed to be used with an external PNP
transistor with a high gain-bandwidth product f
T
to make
a regulator with a very fast transient response, which can
minimize the size of the output capacitor. For a regulator
made of an LT1573 and a D45H11, only one 10µF surface
mount ceramic capacitor at the output is enough for the
regulator to handle the output load varying up to 5A in a
few hundred nanoseconds interval and to remain stable
with a 30pF capacitor in series with a 7.5k resistor between
the V
OUT
and COMP pins. If tighter voltage regulation is
Table 3. LT1573 Thermal Resistance
COPPER AREA
THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm
2
2500mm
2
2500mm
2
80°C/W
1000mm
2
2500mm
2
2500mm
2
80°C/W
225mm
2
2500mm
2
2500mm
2
85°C/W
*Device is mounted on topside.
We can find out the maximum junction temperature of
the LT1573 during normal load operation after we
calculate the maximum power dissipation of the LT1573
from Eq (2). From the previous design example, the
maximum power dissipation of the LT1573 is 0.2W.
From Table 3, we know the thermal resistance from
junction-to-ambient is around 85°C/W. The tempera-
ture difference between junction and ambient is:
(0.25W)(85°C/W) = 21.25°C
If the maximum ambient temperature is specified at
50°C, the maximum junction temperature will be:
T
JMAX
= 50°C + 21.25°C = 71.25°C
The maximum junction temperature must not exceed
the specified 125°C for safe continuous regulator op-
eration.
Thermal Limiting
The thermal shutdown temperature of the LT1573 is
approximately 150°C. The thermal limit of the LT1573 can
be used to protect both the LT1573 and the external PNP
pass transistor. This is accomplished by thermally cou-
pling the LT1573 to the PNP power transistor by locating
the LT1573 as close to the PNP transistor as possible. In
this case, the power dissipation of the power transistor
must be considered in the LT1573 maximum junction
temperature calculation.
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LT1573
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needed during output transients, more capacitance can be
added to the regulator output. If more capacitance is
added to the output, the bandwidth of the regulator is
lowered. A large value compensation capacitor may be
needed to lower the frequency of the compensation zero to
avoid high frequency oscillation. Equal value output
capacitors with different ESR can have different output
transient response. High frequency performance will be
strongly affected by parasitics in the output capacitor and
board layout. Some experimentation with the external
compensation will be required for optimum results.
Shutdown Function
The regulator can be shut down by pulling the SHDN pin
voltage higher than the shutdown threshold (about 1.3V).
The regulator will restart itself if the SHDN is pulled below
the shutdown threshold.The SHDN pin should be tied to
ground if it is not used. The SHDN pin voltage can be
higher than the input voltage. When the SHDN pin voltage
is higher than 2V, the SHDN pin current increases and is
limited by a 20k resistor. Momentarily putting the device
into shutdown also resets the overcurrent latch.
Lower Dropout Voltage or Higher Output
Current Capability
Lower dropout voltage or higher output current capability
can be achieved by paralleling several output PNP transis-
tors as shown in Figure 3. By paralleling output PNP
transistors, the equivalent resistance between the emit-
ters (V
IN
) and collectors (V
OUT
) is lowered or each PNP
transistor sharing the output current now runs at a lower
collector current, which causes the dropout voltage to
decrease. Because the PNP transistors are running at a
lower collector current where the transistor beta is higher,
much more output current can be obtained at a given base
drive current. When paralleling two or more output tran-
sistors, a separate resistor is needed for R
B
and R
D
for
each output transistor. This allows the base drive current
to be split evenly between output transistors, which pro-
motes equal output current sharing. In the specific
example drawn in Figure 3 with two output transistors, the
resistance of R
B1
and R
B2
is now twice the value of the
resistance of R
B
in Figure 2, and the resistance of R
D1
and
R
D2
is twice the value of the resistance of R
D
in Figure 2.
In case of n PNP transistors in parallel, the resistance R
B
COMP
V
OUT
V
IN
DRIVE
FB
LATCH
SHDN
GND
LT1573
+
C
TIME
C
OUT1
C
C
V
IN
R
C
V
OUT
GND
1573 F03
R
B1
R
B2
R
D2
R
D1
R1
R2
LOAD
+
Q
OUT2
Q
OUT1
C
IN
Figure 3. Reduced Dropout Voltage or Increased Output Current
by Paralleling Output PNP Transistors
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LT1573CS8-2.5#PBF

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Analog Devices / Linear Technology
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LDO Voltage Regulators Low Dropout Reg Driver 2.5V
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