ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER
IDT®
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 3
ICS557-06 REV M 070512
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-06 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-06.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
Load Resistors R
L
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-06
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-06 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
