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ISL6273IRZ

P1-P3P4-P6P7-P9P10-P12
4
FN9256.0
March 7, 2006
Typical Operating Performance
FIGURE 1. EFFICIENY vs LOAD CURRENT (V
IN
= 3.6V)
FIGURE 2. V
OUT
vs LOAD CURRENT (V
IN
= 3.6V)
FIGURE 3. EFFICIENCY vs LOAD CURRENT (V
O
= 1.8V) FIGURE 4. V
OUT
vs LOAD CURRENT (V
IN
= 2.7V)
FIGURE 5. I
Q
vs V
IN
(PFM) FIGURE 6. I
Q
vs V
IN
(PWM)
V
O
= 2.5V
V
O
= 1.2V
40
50
60
70
80
90
100
0.1 1 10 100
1000
LOAD CURRENT (mA)
EFFICIENCY (%)
V
O
= 2.8V
3.3
3.31
3.32
3.33
3.34
3.35
3.36
3.37
0.1 1 10 100 1000
LOAD CURRENT (mA)
V
OUT
(V)
V
IN
= 3.6V
40
50
60
70
80
90
100
0.1 1 10 100 1000
LOAD CURRENT (mA)
EFFICIENCY (%)
V
IN
= 2.7V
1.74
1.76
1.78
1.8
1.82
1.84
0.1 1 10 100 1000
LOAD CURRENT (mA)
V
OUT
(V)
V
IN
= 2.7V
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
2.9 3.4 3.9 4.4 4.9 5.4
V
IN
VOLTAGE RANGE (2.9V-5.5V)
INPUT CURRENT (mA)
INPUT CURRENT IN PFM MODE OF 2.8V
0
1
2
3
4
5
6
7
2.9 3.4 3.9 4.4 4.9 5.4
V
IN
VOLTAGE RANGE (2.9V-5.5V)
INPUT CURRENT (mA)
INPUT CURRENT IN PWM MODE OF 2.8V
ISL6273
5
FN9256.0
March 7, 2006
FIGURE 7. SWITCHING FREQUENCY vs V
IN
FIGURE 8. LINE REGULATION (I
O
= 1A)
FIGURE 9. LOAD REGULATION (V
IN
= 3.6V IN PWM MODE) FIGURE 10. SOFT-START
FIGURE 11. PFM MODE (V
IN
= 3V; V
O
= 1.6V; I
O
= 50mA)
FIGURE 12. STEADY-STATE IN PWM MODE (V
IN
= 3.6V;
V
O
= 1.6V; I
O
= 1A)
Typical Operating Performance (Continued)
1.57
1.575
1.58
1.585
1.59
1.595
1.6
1.605
2.7 3.2 3.7 4.2 4.7 5.2
V
IN
(V)
SWITCHING FREQUENCY (MHz)
1.6
1.602
1.604
1.606
1.608
1.61
2.7 3.7 4.7
V
IN
(V)
V
O
(V)
1.59
1.595
1.6
1.605
1.61
0 200 400 600 800 1000
I
O
(mA)
V
O
(V)
ISL6273
6
FN9256.0
March 7, 2006
Pin Descriptions
PVIN
Input supply voltage. Connect a 10μF ceramic capacitor to
power ground.
VCC
Supply voltage for internal analog and digital control circuits,
delivered from PVIN. Bypass with 0.1μF ceramic capacitor to
signal ground.
EN
Regulator enable pin. Enable the output when driven to high.
Shutdown the chip and discharge output capacitor when
driven to low. Do not leave this pin floating.
POR
200ms timer output. At power up or EN HI, this output is a
200ms delayed Power-Good signal for the output voltage.
This output can be reset by a low RSI signal. 200ms starts
when RSI goes to high.
MODE
Mode Selection pin. Connect to logic high or input voltage
VCC for low IQ mode; connect to logic low or ground for
forced PWM mode. Do not leave this pin floating.
PHASE
Switching node connection. Connect to one terminal of
inductor.
PGND
Power ground. Connect all power grounds to this pin
SGND
Analog ground. SGND and PGND should only have one
point connection.
FB
Buck regulator output feedback. Connect to the output
through a resistor divider for adjustable output voltage
(ISL6273-ADJ). For preset output voltage, connect this pin to
the output.
RSI
This input resets the 200ms timer. When the output voltage
is within the PGOOD window, an internal timer is started and
generates a POR signal 200ms later when RSI is low. A low
RSI resets POR and RSI high to low transition restarts the
internal counter if the output voltage is within the window,
otherwise the counter is reset by the output voltage
condition.
Exposed Pad
The exposed pad must be connected to the PGND pin for
proper electrical performance. The exposed pad must also
be connected to as much as possible for optimal thermal
performance.
FIGURE 13. TRANSIENT LOAD TEST (PFM & PWM V
IN
= 3.6V;
V
O
= 1.6V; I
O
= 0A~1A)
FIGURE 14. LOAD TRANSIENT IN PWM MODE (V
IN
= 3.6V;
V
O
= 1.6V; I
O
= 0A~1A)
Typical Operating Performance (Continued)
ISL6273
P1-P3P4-P6P7-P9P10-P12

ISL6273IRZ

Mfr. #:
Buy ISL6273IRZ
Manufacturer:
Renesas / Intersil
Description:
Switching Voltage Regulators W/ANNEAL LW IQ BUCKG W/INTEGRTD FET
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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