3
LTC8043
ELECTRICAL CHARACTERISTICS
V
DD
= 5V, V
REF
= 10V, V
IOUT
= GND
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise specified.
Note 7: To 0.01% for a full-scale change, measured from
falling edge of LD.
Note 8: V
REF
= 0V. DAC register contents changed from all 0s to all 1s or
from all 1s to all 0s.
Note 9: V
REF
= 6V
RMS
at 1kHz. DAC register loaded with all 1s.
Note 10: 10Hz to 100kHz between R
FB
and I
OUT
. Calculation from e
n
=
√4KTRB where: K = Boltzmann constant (J/K°); R = resistance (Ω);
T = resistor temperature (°K); B = bandwidth (Hz).
BLOCK DIAGRAM
W
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: ±0.5LSB = ±0.012% of full scale.
Note 2: Using internal feedback resistor.
Note 3: Guaranteed by design, not subject to test.
Note 4: I
OUT
with DAC register loaded with all 0s.
Note 5: Typical temperature coefficient is 100ppm/°C.
Note 6: I
OUT
load = 100Ω in parallel with 13pF.
40k
10k
40k
20k
40k
20k
40k
20k
40k40k40k
DECODER
BIT 1
(MSB)
BIT 2 BIT 3 BIT 4 BIT 12
(LSB)
CLK
IN
LOAD
V
DD
V
REF
R
FB
I
OUT
SRI
6
GND4
3
2
8043 BD
DAC REGISTER
INPUT 12-BIT SHIFT REGISTER
5
7
8
1
LD
CLK
ALL GRADES
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Inputs
V
IH
Digital Input High Voltage ● 2.4 V
V
IL
Digital Input Low Voltage ● 0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
● 0.001 ±1 µA
C
IN
Digital Input Capacitance V
IN
= 0V,(Note 3) ● 8pF
Timing Characteristics (Note 3)
t
DS
Serial Input to Clock Setup Time ● 30 – 5 ns
t
DH
Serial Input to Clock Hold Time ● 60 25 ns
t
SRI
Serial Input Data Pulse Width ● 80 ns
t
CH
Clock Pulse Width High ● 80 ns
t
CL
Clock Pulse Width Low ● 80 ns
t
LD
Load Pulse Width ● 140 ns
t
ASB
LSB Clocked into Input Register ● 0ns
to Load DAC Register Time
Power Supply
V
DD
Supply Voltage ● 4.75 5 5.25 V
I
DD
Supply Current Digital Inputs = 0V or V
DD
● 100 µA
Digital Inputs = V
IH
or V
IN
● 500 µA
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.