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ISL55010IEZ-T7

P1-P3P4-P6
ISL55010
4
FN6217.0
May 22, 2006
FIGURE 7. OIP3 vs FREQUENCY
FIGURE 8. P1dBm vs FREQUENCY
FIGURE 9. NOISE FIGURE vs FREQUENCY
FIGURE 10. S11 AND S22 vs FREQUENCY
Typical Performance Curves 50Ω environment (Continued)
9
10
11
12
13
0.5 1.0 1.5 2.0 2.5 3.0
Frequency (GHz)
OIP3 (dBm)
0
1
2
3
4
0.5 1.0 1.5 2.0 2.5 3.0
Frequency (GHz)
dBm
0
1
2
3
4
5
6
0.5 1.0 1.5 2.0 2.5 3.0
Frequency (GHz)
NOISE FIGURE (dB)
2
0
20
1.0
0
.
9
0
.
8
0
.
7
0
.
6
0
.
5
0
.
4
0
.
3
0
.
2
0
.
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10
0
.
2
0
.
4
0
.
6
0
.
8
1
.
0
0
.
2
0
.
4
0
.
6
0
.
8
1
.
0
1
.
2
1
.
4
1
.
6
1
.
8
2
.
0
3
.
0
6
.
0
7
.
0
8
.
0
9
.
0
5
0
1
0
5
.
0
4
.
0
2
0
1.0
0
.
9
0
.
8
0
.
7
0
.
6
0
.
5
0
.
4
0
.
3
0
.
2
0
.
1
0
.
2
0
.
4
0
.
6
0
.
8
1
.
0
0
.
2
0
.
4
0
.
6
0
.
8
1
.
0
1
.
2
1
.
4
1
.
6
1
.
8
2
.
0
3
.
0
6
.
0
7
.
0
8
.
0
9
.
0
5
0
1
0
5
.
0
4
.
0
50
RF Café 2002
S22
S11
0.5 GHz
1.0
2.2
3 GHz
0.5 GHz
1.0
2.2
3 GHz
ISL55010
5
FN6217.0
May 22, 2006
Packaging Information
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
176mW
θ
J
A
=
5
6
7
°
C
/
W
S
C
7
0
-
6
POWER DISSIPATION (W)
0.3
0
0
AMBIENT TEMPERATURE (°C)
1507525 10050 12585
0.25
0.1
0.2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
0
0
AMBIENT TEMPERATURE (°C)
1507525 10050 12585
0.15
0.05
ISL55010
6
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6217.0
May 22, 2006
Small Outline Transistor Plastic Packages (SC70-6)
D
e1
E
C
L
e
b
C
L
A2
A
A1
C
L
0.20 (0.008)
M
0.10 (0.004) C
C
-C-
SEATING
PLANE
123
456
E1
C
L
C
VIEW C
VIEW C
L
R1
R
4X θ1
4X θ1
GAUGE PLANE
L1
SEATING
α
L2
C
PLANE
c
BASE METAL
WITH
c1
b1
PLATING
b
P6.049
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.031 0.043 0.80 1.10 -
A1 0.000 0.004 0.00 0.10 -
A2 0.031 0.039 0.00 1.00 -
b 0.006 0.012 0.15 0.30 -
b1 0.006 0.010 0.15 0.25
c 0.003 0.009 0.08 0.22 6
c1 0.003 0.009 0.08 0.20 6
D 0.073 0.085 1.85 2.15 3
E 0.071 0.094 1.80 2.40 -
E1 0.045 0.053 1.15 1.35 3
e 0.0256 Ref 0.65 Ref -
e1 0.0512 Ref 1.30 Ref -
L 0.010 0.018 0.26 0.46 4
L1 0.017 Ref. 0.420 Ref.
L2 0.006 BSC 0.15 BSC
N6 65
R 0.004 - 0.10 -
R1 0.004 0.010 0.15 0.25
α
0
o
8
o
0
o
8
o
-
Rev. 2 9/03
NOTES:
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO203AB.
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
P1-P3P4-P6

ISL55010IEZ-T7

Mfr. #:
Buy ISL55010IEZ-T7
Manufacturer:
Renesas / Intersil
Description:
RF Amplifier ISL59118IRUZ-EVALZ EVAL BRD RHS COMPLI
Lifecycle:
New from this manufacturer.
Delivery:
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