Affects:
PLL
Description:
During a power on reset, if the CLKMOD[1:0] equals 11 (normal PLL mode with crystal
reference), the PLL does not lock and the device never comes out of reset.
Workaround:
When configuring the PLL for normal PLL mode with crystal reference, tie CLKMOD1 to RSTI
and not straight to 3.3V. This allows the PLL to correctly detect the desired operating mode
and lock.
Fix plan:
Currently, there are no plans to fix this.
SECF015: Internal Flash Speculation Address Qualification Incomplete
Errata type:
Silicon
Affects:
Flash controller
Description:
The flash controller uses a variety of advanced techniques, including two-way 32-bit bank
interleaving, address speculation, and pipelining to improve performance. An issue involving a
complex series of interactions between the local flash controller and other memory accesses
(internal SRAM, EIM, or SDRAM) has been uncovered. In rare instances, the interaction
between a non-flash memory access and a flash access can result in incorrect data usage for
a read operation. This may produce unexpected exceptions, incorrect execution, or silent data
corruption.
The problem requires two accesses where the modulo (flash size) address and address mask
configuration are the same for both a flash access and a non-flash access that occur close in
time.
Workaround:
Workaround Step 1 (Always do this): Use FLASHBAR[6] to disable the address speculation
mechanisms of the flash controller. The default configuration (FLASHBAR[6] = 0) enables the
address speculation. If FLASHBAR[6] equals 1, address speculation is disabled. Core
performance may be degraded from 4% – 9%, depending heavily on application code.
NOTE
FLASHBAR[6] is user accessible via the movec instruction.
FLASHBAR[6] always reads back as 0.
NOTE
On MCF528x and MCF521x devices FLASHBAR[6] is already set
to 1 for datecodes XXX0327 and later. The bit still reads back as 0.
Workaround Step 2a (Select one of the step 2 options to use): Construct the device
memory map so the flash and SRAM spaces are disjoint within the modulo-(flash_size)
addresses. In some cases if this approach is selected, the upper portion of the flash memory
might be unused and the SRAM be mapped to this unused flash space.
Consider an example where the flash memory size is 256 Kbytes and the on-chip SRAM size
is 32 Kbytes. If 224 Kbytes or less of flash are used, the SRAM can be based at the upper 32
Kbytes (within the modulo-256 Kbyte address) of the flash address space:
Flash: size = 0x40000, base = 0x0000_0000
RAM: size = 0x08000, base = 0x8003_8000 = RAM_BASE+(256-32) Kbytes
where the flash and SRAM base addresses are unique BA[31:16].
In summary, this approach can be applied if the combined size of the used flash and used
SRAM is less than the total flash size, with the flash contents justified to the lower address
range and the SRAM contents justified to the upper address range.
MCF5282 Chip Errata, Rev 8, 02/2015
Freescale Semiconductor, Inc. 11
