Philips Semiconductors Product data sheet
74F82110-bit bus interface register, non-inverting (3-State)
2
2004 Jul 22
FEATURES
• High speed parallel registers with positive edge-triggered D-type
flip-flops
• High performance bus interface buffering for wide data/address
paths or buses carrying parity
• High-impedance PNP base inputs for reduced loading (20 µA in
HIGH and LOW states)
• I
IL
is 20 µA versus 1000 µA for AM29821 series
• Buffered control inputs to reduce AC effects
• Ideal where high speed, light loading, or increased fan-in as
required with MOS microprocessor
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• Slim Dip 300 mil package
• Broadside pinout compatible with AMD AM 29821
• Outputs sink 64 mA and source 24 mA
DESCRIPTION
The 74F821 bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data
width for wider data/address paths of buses carrying parity.
The 74F821 is a buffered 10-bit wide version of the popular
74F374/74F534 functions.
TYPE
TYPICAL f
max
TYPICAL SUPPLY CURRENT
(TOTAL)
74F821 180 MHz 75 mA
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
1312
10
11
9
8
7
6
5
4
3
2
1
GND
OE
CP
Q0
Q3
Q4
Q5
Q6
V
CC
Q7
Q1
Q2
Q8
Q9
D0
D3
D4
D5
D6
D7
D1
D2
D8
D9
SF00482
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Dn Data inputs 1.0/1.0 20 µA/0.6 mA
CP Clock input 1.0/1.0 20 µA/0.6 mA
OE Output enable input (active-LOW) 1.0/3.0 20 µA/1.8 mA
Qn Data outputs 1200/106.7 24 mA/64 mA
NOTE: One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
ORDERING INFORMATION
Commercial range: V
CC
= 5 V
±
10 %; T
amb
= 0
°
C to +70
°
C
Type number
Package
Name Description Version
N74F821D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
N74F821N DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1
