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8 www.ixysic.com R02
CPC7601
2. Functional Description
The CPC7601 takes a serial stream of input data
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of each
shift register is shifted through from SR(n) to SR(n+1).
A high data bit, a “1,” represents an ON switch; a low
data bit, a “0,” represents an OFF switch. Data is input
and shifted through the internal shift register until all
sixteen shift register positions, SR0 through SR15, are
in the desired state.
D
IN
: The data-in line presents data bits to be shifted
through the internal shift register. The last bit into the
shift register is the SW0 control bit.
CLK: The clock signal's rising edge is associated only
with shifting data into and through the shift register.
CL: The clear line overrides all other inputs. When CL
is high, the shift register is asynchronously cleared to
all “0”s and all latches are set low, which causes all
output switches to be turned OFF immediately. When
CL is low, all output switches remain in whatever state
they are in, ON or OFF, in response to CLK, latch
inputs, and the LE
signal.
LE
: latch enable controls the state of the latches and
thus the state of the eight switches. If LE
is high, then
the latches do not change states, but retain their most
recent status: either ON or OFF. With LE
high, input
data and CLK have no effect on the state of the output
switches. If LE
is low, then all latch outputs and their
switch states follow the inputs from the shift register.
LE
is overridden by CL: regardless of LE’s state, CL
clears the latches. See “Truth Table” on page 9.
Note that holding LE
active while clocking in new data
will cause the outputs to toggle with the shifting data.
D
OUT
: The data-out pin is the output of SR15. After
sixteen clock pulses, the first bit of sixteen shifted input
data bits is output at SR15, and appears on D
OUT
.
SW0 - SW15: The CPC7601 provides sixteen
high-voltage SPST output switches with a nominal
small-signal on-resistance of 25 The two
connections of each switch are not polarity-sensitive.
V
PP
and V
NN
: Voltage inputs to the level shifters for
each switch channel that translate the voltage level of
the latch output signals to an appropriate level for the
voltages being switched. The high-voltage output
switches are turned on and off in response to data
sent into the latches from the shift register: “0” turns a
switch OFF, “1” turns a switch ON.
Two or more CPC7601 devices can be cascaded to
form an n-switch arrangement. The D
OUT
pin of the
first is connected to the D
IN
pin of the next in the
series. All devices are connected to the same clock
(CLK) signal. LE
of all devices would normally be
connected, as would CL, but this is not necessary.
The first data bit applied to D
IN
of the CPC7601,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in line
after the application of a full clocking sequence of
sixteen clock pulses. Setting the serial I/O device to
output the most significant bit (MSB) first, results in the
MSB appearing on SW15 of the last device in line after
a full clocking sequence.
CL
D
IN
CLK
LE
SW0
SW15
SW0
SW15
SW0
SW15
D
OUT
LE
CL
D
IN
CLK
D
OUT
LE
CL
D
IN
CLK
D
OUT
LE
CL
D
IN
CLK
CPC7601
CPC7601
CPC7601
