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LT6556IGN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LT6556
7
6556f
PI FU CTIO S
UUU
IN1A (Pin 1): Channel 1 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
DGND (Pin 2): Digital Ground Reference for Enable Pin.
This pin is normally connected to ground.
IN2A (Pin 3): Channel 2 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
VREF (Pin 4): Voltage Reference for Input Clamping. This
is the tap to an internal voltage divider that defi nes mid-
supply. It is normally connected to ground in dual supply,
DC coupled applications.
IN3A (Pin 5): Channel 3 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 6): Analog Ground for Isolation between IN3A
and IN1B. AGND pins have ESD protection and should not be
connected to potentials outside the power supply range.
IN1B (Pin 7): Channel 1 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 8): Analog Ground for Isolation between IN1B
and IN2B. AGND pins have ESD protection and should not be
connected to potentials outside the power supply range.
IN2B (Pin 9): Channel 2 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 10): Analog Ground for Isolation between
IN2B
and IN3B. AGND pins have ESD protection and
should not be connected to potentials outside the power
supply range.
IN3B (Pin 11): Channel 3 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
V– (Pin 12):
Negative Supply Voltage. V
–
pins are not in-
ternally connected to each other and must all be connected
externally. Proper supply bypassing is necessary for best
performance. See the Applications Information section.
V+ (Pins 13, 14, 24): Positive Supply Voltage. V
+
pins
are not internally connected to each other and must all
be connected externally. Proper supply bypassing is
necessary for best performance. See the Applications
Information section.
V– (Pin 15): Negative Supply Voltage for Channel 3 Output
Stage. V
–
pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
OUT3 (Pin 16): Channel 3 Output. It is the buffered output
of the selected Channel 3 input.
V+ (Pin 17): Positive Supply Voltage for Channels 2 and
3 Output Stages. V
+
pins are not internally connected to
each other and must all be connected externally. Proper
supply bypassing is necessary for best performance. See
the Applications Information section.
OUT2 (Pin 18): Channel 2 Output. It is the buffered output
of the selected Channel 2 input.
V– (Pin 19): Negative Supply Voltage for Channels 1 and
2 Output Stages. V
–
pins are not internally connected to
each other and must all be connected externally. Proper
supply bypassing is necessary for best performance. See
the Applications Information section.
OUT1 (Pin 20): Channel 1 Output. It is the buffered output
of the selected Channel 1 input.
V+ (Pin 21): Positive Supply Voltage for Channel 1 Output
Stage. V
+
pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
SEL
⎯
A/B (Pin 22): Select Pin. This high impedance pin
selects which set of inputs are sent to the output pins.
When the pin is pulled low, the A inputs are selected. When
the pin is pulled high, the B inputs are selected.
⎯
E
⎯
N (Pin 23): Enable Control Pin. An internal pull-up resistor
of 46k defi nes the pin’s impedance and will turn the part
off if the pin is unconnected. When the pin is pulled low,
the amplifi ers are enabled.
Exposed Pad (Pin 25, QFN Only): The Exposed Pad is
V
–
and must be soldered to the PCB. It is internally con-
nected to the QFN Pin 4, V
–
.
(GN24 Package)
LT6556
8
6556f
APPLICATIO S I FOR ATIO
WUU
U
Power Supplies
The LT6556 is optimized for ±5V supplies but can be op-
erated on as little as ±2.25V or a single 4.5V supply and
as much as ±6V or a single 12V supply. Internally, each
supply is independent to improve channel isolation. Do
not leave any supply pins disconnected or the part may
not function correctly!
Enable/Shutdown
The LT6556 has a shutdown mode controlled by the
⎯
E
⎯
N
pin and referenced to the DGND pin. If the amplifi er will be
enabled at all times, the
⎯
E
⎯
N pin can be connected directly
to DGND. If the enable function is desired, either driving
the pin above 2V or allowing the internal 46k pull-up
resistor to pull the
⎯
E
⎯
N pin to the top rail will disable the
amplifi er. When disabled, the output will become very
high impedance. Supply current into the amplifi er in the
disabled state will be:
I
VV
k
VV
k
S
EN
=+
+
+
–
–
–
46 80
It is important that the following constraints on the DGND,
⎯
E
⎯
N and SEL pins are always followed:
V
+
– V
DGND
≥ 4.5V
-0.5V ≤ V
⎯
E
⎯
N
– V
DGND
≤ 5.5V
V
SEL
– V
DGND
≤ 8V
In dual supply cases where V
+
is less than 4.5V, DGND
should be connected to a potential below ground, such as
V
–
. Since the
⎯
E
⎯
N and SEL pins are referenced to DGND, they
may need to be pulled below ground in those cases. However,
in order to protect the internal enable circuitry, the
⎯
E
⎯
N pin
should not be forced more than 0.5V below DGND.
In single supply applications above 5.5V, an additional
resistor may be needed from the
⎯
E
⎯
N
pin to DGND if the
pin is ever allowed to fl oat. For example, on a 12V single
supply, a 33k resistor would protect the pin from fl oating
too high while still allowing the internal pull-up resistor
to disable the part.
On dual ±2.25V supplies, connecting the DGND pin to V
–
is
the only way of ensuring that V
+
– V
DGND
≥ 4.5V.
The enable/disable times of the LT6556 are fast when
driven with a logic input. Turn on (from 50%
⎯
E
⎯
N
input to
50% output) typically occurs in less than 50ns. Turn off
is slower, but is typically below 500ns.
Channel Select
The SEL pin uses the same internal threshold as the
⎯
E
⎯
N
pin and is also referenced to DGND. When the pin is logic
low, the channel A inputs are passed to the output. When
the pin is logic high, the channel B inputs are passed to
the output. The pin should not be fl oated but can be tied
to DGND to force the outputs to always be channel A or
to V
+
(when less than 8V) to force the outputs to always
be channel B.
Truth Table
SEL
⎯
A/B
⎯
E
⎯
N OUT
0 0 IN A
1 0 IN B
X 1 OFF
Input Considerations
The LT6556 uses input clamps referenced to the V
REF
pin
to prevent damage to the input stage on the unselected
channel. Three transistors in series limit the input voltage to
within three diode drops (±) from V
REF
. V
REF
is nominally
set to half of the sum of the supplies by the 40k resistors.
A simplifi ed schematic is shown in Figure 1.
V
REF
40k
40k
6556 F01
V
+
V
–
IN
Figure 1. Simplifi ed Schematic of V
REF
Pin and Input Clamping
LT6556
9
6556f
To improve clamping, the pin’s DC impedance should be
minimized by connecting the V
REF
pin directly to ground
in the symmetric dual supply case with a common mode
voltage of 0V. If the common mode voltage is not centered
at ground or the input voltage exceeds plus or minus three
diodes from ground, an external resistor to either supply
can be added to shift the V
REF
voltage to the desired level.
The only way to cover the full input voltage range of V
–
+
1V to V
+
– 1V is to shift V
REF
up or down.
The V
REF
pin can also be directly driven with a DC source.
Figure 2 shows the effect of the clamp on input current
when sweeping input voltage with various V
REF
pin volt-
ages. Bypassing the V
REF
pin is not necessary.
INPUT VOLTAGE (V)
–4
INPUT CURRENT (μA)
0
100
4
6556 F02
–100
–250
–200
–2
0
2
–3
–1
1
3
250
200
–50
50
–150
150
T
A
= 25°C
V
S
= ±5V
V
REF
= 2V
V
REF
= 1V
V
REF
= 0V
V
REF
= –1V
V
REF
= –2V
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to less
than ±10mA. Continuing to drive the input beyond the
output limit can result in increased current drive and
slightly increased swing, but will also increase supply
current and may result in delays in transient response
at larger levels of overdrive.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
benefi t from the very high speed and very low crosstalk of
the LT6556. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input traces must be run over a distance of
several centimeters, they should use a controlled imped-
ance with either series or shunt terminations (nominally
50Ω or 75Ω) to maintain signal fi delity.
Care should be taken to minimize capacitance on the
LT6556’s output traces by increasing spacing between
traces and adjacent metal and by eliminating metal planes
in underlying layers. To drive cable or traces longer than
several centimeters, using the LT6555 with its fi xed gain
of+2 in conjunction with series and load termination resis-
tors may provide better results.
A plot of AC performance driving a 1k load with various
trace lengths is shown in Figure 3. All data is from a 4-layer
board with 2oz copper, 18mil of board layer thickness to
the ground plane, a trace width of 12mils and spacing to
adjacent metal of 18mils. The 0.2cm output trace places
the 1k resistor as close to the part as possible, while the
other curves show the load resistor consecutively further
away. The worst case, 4cm, trace has almost 10pF of
parasitic capacitance.
FREQUENCY (MHz)
0.1
AMPLITUDE (dB)
6
4
2
0
–2
–4
–6
1
10 100 1000
6556 F03
4cm TRACE
0.2cm TRACE
2cm TRACE
V
S
= ±5V
V
OUT
= 200mV
P-P
R
L
= 1k
T
A
= 25°C
Figure 3. Response vs Output Trace Length
APPLICATIO S I FOR ATIO
WUU
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Figure 2. Input Current vs Input Voltage
at Different V
REF
Voltages
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LT6556IGN#PBF

Mfr. #:
Buy LT6556IGN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Video Switch ICs 750MHz Gain of 1 3x 2:1Video Multxer
Lifecycle:
New from this manufacturer.
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