Datasheet
10/13
BU42xx series BU43xx series
TSZ02201-0R7R0G300050-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
18.Dec.2012 Rev.005
www.rohm.com
TSZ22111・15・001
●Application Information
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the V
DD pins reaches the applicable threshold voltage, the VouT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. BU42xx and BU43xx series have delay time function
which set t
PLH (Output “Low”Æ”High”) using an external capacitor (CCT). Because the BU42xx series uses an open drain
output type, it is necessary to connect a pull-up resistor to V
DD or another power supply if needed [The output “High”
voltage (V
OUT) in this case becomes VDD or the voltage of the other power supply].
Fig.15 (BU42xx series Internal Block Diagram) Fig.16 (BU43xx type Internal Block Diagram)
Setting of Detector Delay Time
The delay time of this detector IC can be set at the rise of VDD by the capacitor connected to C
T
terminal.
Delay time at the rise of V
DD t
PLH
:Time until when VouT rises to 1/2 of VDD after VDD rises up and beyond the release
voltage(V
DET
+V
DET
)
T
PLH
=-1×C
CT
×R
CT
×ln
C
CT
: C
T
pin Externally Attached Capacitance V
CTH
: C
T
pin Threshold Voltage(P.3 VCTH refer.)
R
CT
: C
T
pin Internal Impedance(P.3 R
CT
refer.) ln: Natural Logarithm
Reference Data of Falling Time (t
PHL
) Output
Examples of Falling Time (t
PHL
) Output
Part Number t
PHL
[µs]
BU4245 275.7
BU4345 359.3
* This data is for reference only.
The figures will vary with the application, so please confirm the actual operating conditions before use.
Timing Waveforms
Example: The following shows the relationship between the input voltage VDD, the C
T
Terminal Voltage VCT and the output
voltage
VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are shown in
Fig.15 and 16).
① When the power supply is turned on, the output is unstable from
after over the operating limit voltage (V
OPL) until tPHL. Therefore, it is
possible that the reset signal is not outputted when the rise time of
V
DD is faster than tPHL.
② When V
DD is greater than VOPL but less than the reset release
voltage (V
DET+VDET), the CT terminal (VCT) and output (VOUT)
voltages will switch to L.
③ If V
DD exceeds the reset release voltage (VDET+VDET), then VOUT
switches from L to H (with a delay to the CT terminal).
④ If V
DD drops below the detection voltage (VDET) when the power
supply is powered down or when there is a power supply fluctuation,
V
OUT switches to L (with a delay of tPHL).
⑤ The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (V
DET). The system
is designed such that the output does not toggle with power supply
fluctuations within this hysteresis width, preventing malfunctions due
to noise.
Vref
V
DD
GND
CT
R1
R2
R3
Q3
Q1
V
OUT
RESET
V
DD
Vref
V
DD
GND
CT
R1
R2
R3
Q3
Q2
V
OUT
RESET
Q1
V
DD
V
DD
-V
CTH
V
DD
VDD
VDET+ΔVDET
VDET
VOPL
0V
1/2 VDD
tPHL
①
tPLH
tPHL
tPLH
② ③ ④
⑤
VCT
VOUT
Fig.17 Timing Waveforms
