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MAX5422ETA+T

P1-P3P4-P6P7-P9P10-P11
Detailed Description
The MAX5422/MAX5423/MAX5424 contain a resistor
array with 255 resistive elements. The MAX5422 has a
total end-to-end resistance of 50kΩ; the MAX5423 has
an end-to-end resistance of 100kΩ; and the MAX5424
has an end-to-end resistance of 200kΩ. The
MAX5422/MAX5423/MAX5424 allow access to the high,
low, and wiper terminals for a standard voltage-divider
configuration. H, L, and W can be connected in any
desired configuration as long as their voltages fall
between GND and V
DD
.
A simple, 3-wire, SPI serial interface moves the wiper
among the 256 tap points. The nonvolatile memory
stores the wiper position and recalls the stored wiper
position upon power-up. The nonvolatile memory is
guaranteed for 50 years for wiper data retention and up
to 200,000 wiper store cycles.
Analog Circuitry
The MAX5422/MAX5423/MAX5424 consist of a resistor
array with 255 resistive elements; 256 tap points are
accessible to the wiper, W, along the resistor string
between H and L. Select the wiper tap point by pro-
gramming the potentiometer through the 3-wire (SPI)
interface. Eight data bits, and a control byte program
the wiper position. The H and L terminals of the
MAX5422/MAX5423/MAX5424 are similar to the two
end terminals of a mechanical potentiometer. The
MAX5422/MAX5423/MAX5424 feature power-on reset
circuitry that loads the wiper position from the non-
volatile memory at power-up.
Digital Interface
The MAX5422/MAX5423/MAX5424 use a 3-wire, SPI-
compatible, serial data interface (Figure 1 and 2). This
write-only interface contains three inputs: chip-select
MAX5422/MAX5423/MAX5424
256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
_______________________________________________________________________________________ 7
PIN NAME FUNCTION
1V
DD
Power-Supply Input. Bypass V
DD
with a 0.1µF capacitor from V
DD
to GND.
2 SCLK Serial-Interface Clock Input
3 DIN Serial-Interface Data Input
4 CS Active-Low Digital-Input Chip Select
5 GND Ground
6L
Low Terminal. The voltage at L can be greater than or less than the voltage at H. Current can flow into or
out of L.
7 W Wiper Terminal
8H
High Terminal. The voltage at H can be greater than or less than the voltage at L. Current can flow into or
out of H.
— EP Exposed Pad. The exposed pad is not internally connected. Connect to GND or leave floating.
Pin Description
SCLK
CS
DIN
t
CS0
t
DS
t
CL
t
CH
t
DH
t
CP
t
CSH
t
CS1
t
CSW
t
CSS
Figure 1. Digital Interface and Timing Diagram
MAX5422/MAX5423/MAX5424
(CS), data clock (SCLK), and data in (DIN). Drive CS
low to enable the serial interface and clock data syn-
chronously into the shift register on each SCLK rising
edge.
The WRITE commands (C1, C0 = 00 or 01) require 16
clock cycles to clock in the command and data (Figure
2a). The COPY commands (C1, C0 = 10, 11) can use
either eight clock cycles to transfer the command bits
(Figure 2b) or 16 clock cycles with 8 data bits that are
disregarded by the device (Figure 2a).
After loading data into the shift register, drive CS high
to latch the data into the appropriate potentiometer
control register and disable the serial interface. Keep
CS low during the entire serial-data stream to avoid
corruption of the data.
The serial-data timing for the potentiometer is shown in
Figures 1 and 2.
256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
8 _______________________________________________________________________________________
CLOCK EDGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Bit name — — C1 C0 — — — — D7 D6 D5 D4 D3 D2 D1 D0
Write wiper register 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
Write NV register 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
Copy wiper register to NV
register
00100000————————
Copy NV register to wiper
register
00110000————————
Table 1. Register Map
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3 D2 D1 D0C1 C0
SCLK
DIN
A) 16-BIT COMMAND/DATA WORD
12345678
C1 C0
SCLK
DIN
B) 8-BIT COMMAND WORD
CS
CS
Figure 2. Digital-Interface Format
Write Wiper Register
Data written to this register (C1, C0 = 00) controls the
wiper positions. The 8 data bits (D7 to D0) indicate the
position of the wiper. For example, if DIN = 0000 0000,
the wiper moves to the position closest to L. If DIN =
1111 1111, the wiper moves closest to H.
This command writes data to the volatile random
access memory (RAM), leaving the NV registers
unchanged. When the device powers up, the data
stored in the NV registers transfers to the volatile wiper
register, moving the wiper to the stored position.
Write NV Register
The “write NV register” command (C1, C0 = 01) stores
the position of the wipers to the NV registers for use at
power-up. Alternatively, the “copy wiper register to NV
register” command writes to the NV register. Writing to the
NV registers, does not affect the position of the wipers.
Copy Wiper Register to NV Register
The “copy wiper register to NV register” command (C1,
C0 = 10) stores the current position of the wiper to the
NV register for use at power-up.
Copy NV Register to Wiper Register
The “copy NV register to wiper register” (C1, C0 = 11)
restores the wiper position to the current value stored in
the NV register.
Standby Mode
The MAX5422/MAX5423/MAX5424 feature a low-power
standby mode. When the device is not being pro-
grammed, it enters into standby mode and supply cur-
rent drops to 0.5µA (typ).
Nonvolatile Memory
The internal EEPROM consists of a nonvolatile register
that retains the last value stored prior to power-down.
The nonvolatile register is programmed to midscale at
the factory. The nonvolatile memory is guaranteed for
50 years for wiper data retention and up to 200,000
wiper write cycles.
Power-Up
Upon power-up, the MAX5422/MAX5423/MAX5424
load the data stored in the nonvolatile wiper register
into the volatile wiper register, updating the wiper posi-
tion with the data stored in the nonvolatile wiper regis-
ter. This initialization period takes 10µs.
Applications Information
The MAX5422/MAX5423/MAX5424 are intended for cir-
cuits requiring digitally controlled adjustable resis-
tance, such as LCD contrast control (where voltage
biasing adjusts the display contrast), or programmable
filters with adjustable gain and/or cutoff frequency.
Positive LCD Bias Control
Figures 3 and 4 show an application where a voltage-
divider or variable resistor is used to make an
adjustable, positive LCD-bias voltage. The op amp pro-
vides buffering and gain to the resistor-divider network
made by the potentiometer (Figure 3) or to a fixed
resistor and a variable resistor (see Figure 4).
MAX5422/MAX5423/MAX5424
256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
_______________________________________________________________________________________ 9
V
OUT
30V
5V
W
H
L
MAX5422
MAX5423
MAX5424
Figure 3. Positive LCD-Bias Control Using a Voltage-Divider
V
OUT
30V
5V
W
H
L
MAX5422
MAX5423
MAX5424
Figure 4. Positive LCD-Bias Control Using a Variable Resistor
P1-P3P4-P6P7-P9P10-P11

MAX5422ETA+T

Mfr. #:
Buy MAX5422ETA+T
Manufacturer:
Maxim Integrated
Description:
Digital Potentiometer ICs 256-Tap Nonvolatile SPI-Interface
Lifecycle:
New from this manufacturer.
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