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NB6L239MNR2G

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 6
1 Publication Order Number:
NB6L239/D
NB6L239
2.5V / 3.3V Any Differential
Clock IN to Differential
LVPECL OUT ÷1/2/4/8,
÷2/4/8/16 Clock Divider
Description
The NB6L239 is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive a pair of differential
LVPECL outputs. (More device information on page 7). The
NB6L239 is a member of the ECLinPS MAX™ Family of the high
performance clock products.
Features
• Maximum Clock Input Frequency, 3.0 GHz
• CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL
• EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS
• Rise/Fall Time 65 ps Typical
• < 10 ps Typical Output−to−Output Skew
• Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
• Internal 50 W Termination Provided
• Random Clock Jitter < 1 ps RMS
• QA B1 Edge Aligned to QBBn Edge
• Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
• Master Reset for Synchronization of Multiple Chips
• V
BBAC
Reference Output
• Synchronous Output Enable/Disable
• These Devices are Pb−Free and are RoHS Compliant
CLK
CLK
EN
Figure 1. Simplified Logic Diagram
QB
QB
MR
QA
QA
SELB1
SELB0
SELA1
SELA0
VT
+
B1
B2
B4
B8
A
B2
B4
B8
B16
B
V
BBAC
50 W
50 W
MARKING DIAGRAM*
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
1
16
NB6L
239
ALYWG
G
1
NB6L239
http://onsemi.com
2
SELA0
Figure 2. Pinout: QFN−16 (Top View)
CLK
CLK
V
BBAC
VT
EN
QA
QB
SELB1
QA
V
EE
QB
1
2
3
4
5678
9
10
11
12
13141516
V
CC
SELA1
SELB0
NB6L239
MR
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VT
Internal 100 W Center−Tapped Termination Pin for CLK and CLK.
2 CLK LVPECL, CML, LVDS,
HCSL, HSTL Input
Noninverted Differential CLOCK Input.
3 CLK LVPECL, CML, LVDS,
HCSL, HSTL Input
Inverted Differential CLOCK Input.
4 V
BBAC
Output Voltage Reference for Capacitor Coupled Inputs, Only.
5 EN* LVCMOS/LVTTL Input Synchronous Output Enable
6 SELB0* LVCMOS/LVTTL Input Clock Divide Select Pin
7 SELB1* LVCMOS/LVTTL Input Clock Divide Select Pin
8 V
EE
Power Supply Negative Supply Voltage
9 QB LVPECL Output
Inverted Differential Output. Typically terminated with 50 W resistor to V
CC
− 2.0 V.
10 QB LVPECL Output
Noninverted Differential Output. Typically terminated with 50 W resistor to V
CC
− 2.0 V.
11 QA LVPECL Output
Inverted Differential Output. Typically terminated with 50 W resistor to V
CC
− 2.0 V.
12 QA LVPECL Output
Noninverted Differential Output. Typically terminated with 50 W resistor to V
CC
− 2.0 V.
13 V
CC
Power Supply Positive Supply Voltage.
14 SELA1* LVCMOS/LVTTL Input Clock Divide Select Pin
15 SELA0* LVCMOS/LVTTL Input Clock Divide Select Pin
16 MR** LVCMOS/LVTTL Input Master Reset Asynchronous, Default Open High, Asserted LOW
EP Power Supply (OPT) The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The pad is electrically connected to the die, and
is recommended to be electrically and thermally connected to V
EE
on the PC board.
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
NB6L239
http://onsemi.com
3
CLK
CLK
EN
Figure 3. Logic Diagram
QB
QB
V
CC
V
EE
MR
R
R
QA
QA
SELB1
SELB0
SELA1
SELA0
V
BBAC
B1
B2
B4
B8
B2
B4
B8
B16
VT
50 W
50 W
+
+
A
B
Table 2. FUNCTION TABLE
CLK EN* MR** FUNCTION
X
L
H
X
H
H
L
Divide
Hold Q
Reset Q
Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS
SELA1* SELA0* QA Outputs
L
L
H
H
L
H
L
H
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS
SELB1* SELB0* QB Outputs
L
L
H
H
L
H
L
H
Divide by 2
Divide by 4
Divide by 8
Divide by 16
= Low−to−High Transition
= High−to−Low Transition
X = Don’t Care
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
P1-P3P4-P6P7-P9P10-P12

NB6L239MNR2G

Mfr. #:
Buy NB6L239MNR2G
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 2.5V/3.3V LVPECL Out Dual Bank
Lifecycle:
New from this manufacturer.
Delivery:
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