CAT28F010
13
Doc. No. MD-1019, Rev. G© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
28F010 F10
ADDRESSES
WE (E)
OE (G)
CE (W)
DATA (I/O)
V
CC
V
PP
t
WC
t
WC
t
RC
t
AVEL
t
ELAX
t
WLEL
t
WLEL
t
EHQZ
t
DF
t
GHEL
t
EHEL
t
EHEH
t
EHGL
t
ELEH
HIGH-Z
DATA IN
= 40H
DATA IN
DATA IN
= C0H
VALID
DATA OUT
t
EHDX
t
OLZ
t
OE
t
OH
t
LZ
t
CE
t
VPEL
V
PPH
V
PPL
0V
5.0V
V
CC
POWER-UP
& STANDBY
SETUP PROGRAM
COMMAND
LATCH ADDRESS
& DATA
PROGRAMMING
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
CC
POWER-DOWN/
STANDBY
t
WLEL
t
EHWH
t
EHWH
t
EHWH
t
ELEH
t
DVEH
t
DVEH
t
DVEH
t
EHDX
t
EHDX
(W)
(E)
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify V
CC
. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Abort/Reset
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
POWER UP/DOWN PROTECTION
The CAT28F010 offers protection against inadvertent
programming during V
PP
and V
CC
power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, V
PP
and V
CC
may power up in any order. Additionally V
PP
may be
hardwired to V
PPH
independent of the state of V
CC
and
any power up/down cycling. The internal command
register of the CAT28F010 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between V
CC
and V
SS
and V
PP
and V
SS
. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 8. Alternate A.C. Timing for Program Operation
