9
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE
TABLE 3 – PORT B ENABLE FUNCTION TABLE
CSB W/RB ENB SIZ1, SIZ0 CLKB Data B (B0-B35) I/O Port Function
H X X X X Input None
L H L X X Input None
L H H One, both LOW ↑ Input None
L H H Both HIGH ↑ Input Mail2 write
L L L One, both LOW X Output None
L L H One, both LOW ↑ Output FIFO read
L L L Both HIGH X Output None
L L H Both HIGH ↑ Output Mail1 read (set MBF1 HIGH)
FUNCTIONAL DESCRIPTION
RESET (RST)
The IDT72V3613 is reset by taking the Reset (RST) input LOW for at least
four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of the FIFO and forces the
Full Flag (FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW,
and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags
(MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH
transitions of CLKA. The device must be reset after power up before data is
written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the value selected by the Flag Select (FS0,
FS1) inputs. The values that can be loaded into the register are shown in Table
1. See Figure 5 for relevant FIFO Reset and preset value loading timing diagram.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by the port-A Chip
Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35 outputs are active when both CSA and W/RA are LOW.
CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Function
H X X X X Input None
L H L X X Input None
LHHL↑ Input FIFO write
LHHH↑ Input Mail1 write
L L L L X Output None
LLHL↑ Output None
L L L H X Output None
LLHH↑ Output Mail2 read (set MBF2 HIGH)
TABLE 2 – PORT A ENABLE FUNCTION TABLE
ALMOST-FULL AND
FS1 FS0 RST ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
HH↑ 16
HL↑ 12
LH↑ 8
LL↑ 4
TABLE 1 – FLAG PROGRAMMING
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FF is HIGH (see Table 2). The relevant FIFO write timing diagram
can found in Figure 6.
The state of the port B data (B0-B35) outputs is controlled by the port B
Chip Select (CSB) and the port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either CSB or W/RB is HIGH. The
B0-B35 outputs are active when both CSB and W/RB are LOW. Data is read
from the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when
CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or
SIZ1 is LOW (see Table 3). Relevant FIFO read timing diagrams together with
Bus-Matching, Endian select and Byte-swapping operation can be found in
Figures 7, 8 and 9.
The setup and hold-time constraints to the port clocks for the port Chip Selects
(CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write
and read operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/
Read select can change states during the setup and hold time window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through two flip-flop stages.
This is done to improve the flags’ reliability by reducing the probability of
metastable events on their outputs when CLKA and CLKB operate asynchro-
nously to one another. FF and AF are synchronized to CLKA. EF and AE are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
level of FIFO fill.
EMPTY FLAG (EF)
The FIFO Empty Flag is synchronized to the port clock that reads data from
its array (CLKB). When the EF is HIGH, new data can be read to the FIFO output
register. When the EF is LOW, the FIFO is empty and attempted FIFO reads
