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72V3613L20PF8
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
22
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
NOTE
:
1
.
Port-A parity generation off (PGA = LOW).
Figure 15. Timing for Mail2 Register and
MBF2
MBF2
MBF2
MBF2
MBF2
Flag
NOTE:
1.
CSA
= LOW and ENA = HIGH.
Figure 16. ODD/
EVEN
EVEN
EVEN
EVEN
EVEN
, W/
R
R
R
R
R
A, MBA, and PGA to
PEFA
PEFA
PEFA
PEFA
PEFA
Timing
4661 drw 15
CLKB
ENB
B0 - B35
SIZ1,
SIZ0
CSB
W/
R
B
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/
R
A
W1
t
ENS
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
ENS
t
ENH
t
DIS
t
EN
t
PMR
W1 (Remains valid in Mail2 Register after read)
t
SZS
t
SZH
t
ENS
t
ENH
t
ENS
t
ENH
ODD/
EVEN
PEFA
PGA
MBA
W/
R
A
4661 drw 16
Valid
Valid
Valid
Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
23
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
Figure 19. Parity Generation Timing when Reading from the Mail1 Register
NOTE:
1
.
ENA = HIGH.
Figure 18. Parity Generation Timing when Reading from the Mail2 Register
NOTE:
1
.
ENB = HIGH.
Figure 17. ODD/
EVEN
EVEN
EVEN
EVEN
EVEN
, W/
R
R
R
R
R
B, SIZ1, SIZ0, and PGB to
PEFB
PEFB
PEFB
PEFB
PEFB
Timing
NOTE:
1.
CSB
= LOW and ENB = HIGH.
ODD/
EVEN
PEFB
PGB
SIZ1,
SIZ0
W/
R
B
4661 drw 17
Valid
Valid
Valid
Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
ODD/
EVEN
A8, A17,
A26, A35
PGA
MBA
W/
R
A
CSA
4661 drw 18
Mail2 Data
Generated Parity
Generated Parity
Mail2 Data
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
ODD/
EVEN
B8, B17,
B26, B35
PGB
SIZ1,
SIZ0
W/
R
B
CSB
4661 drw 19
Mail1
Data
Generated Parity
Generated Parity
Mail1 Data
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
24
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
NOTE:
1
. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms
4661 drw 20
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330
Ω
3.3V
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
≈
3V
1.5 V
1.5 V
1.5 V
1.5 V
OH
≈
OV
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
72V3613L20PF8
Mfr. #:
Buy 72V3613L20PF8
Manufacturer:
Description:
IC FIFO CLOCK 64X36 20NS 120TQFP
Lifecycle:
New from this manufacturer.
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