IDT8P34S1106NLGI Data Sheet 1:6 LVDS Output 1.8V Fanout Buffer
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014 4 ©2014 Integrated Device Technology, Inc.
Table 3B. Differential Input Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current CLK, nCLK V
IN
= V
DD
= 1.89V 150 µA
I
IL
Input Low Current
CLK V
IN
= 0V, V
DD
= 1.89V -10 µA
nCLK V
IN
= 0V, V
DD
= 1.89V -150 µA
V
REF
Reference Voltage for Input
Bias
Note1.
1. V
REF
specification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.
I
REF
= +100µA, V
DD
= 1.8V 0.9 1.30 V
V
PP
Peak-to-Peak Voltage V
DD
= 1.89V 0.2 1.0 V
V
CMR
Common Mode Input Voltage
Note2.
Note3.
2. Common mode input voltage is defined as crosspoint voltage.
3. V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
0.9 V
DD
– (V
PP
/2) V
Table 3C. LVDS DC Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage Outputs Loaded with 100 247 350 454 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.0 1.23 1.4 V
V
OS
V
OS
Magnitude Change 50 mV
Note3.
IDT8P34S1106NLGI Data Sheet 1:6 LVDS Output 1.8V Fanout Buffer
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014 5 ©2014 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 4. AC Electrical Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note1.
1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Input
Frequency
CLK, nCLK 1.2 GHz
V/t
Input
Edge Rate
CLK, nCLK 1.5 V/ns
t
PD
Propagation Delay
Note2.
2. Measured from the differential input crossing point to the differential output crossing point
CLK, nCLK to any Qx, nQx
for V
PP
= 0.4V
190 290 400 ps
tsk(o) Output Skew
Note3.
Note4.
3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
4. This parameter is defined in accordance with JEDEC Standard 65.
20 40 ps
tsk(p) Pulse Skew f
REF
= 100MHz 4 20 ps
tsk(pp) Part-to-Part Skew
Note5.
5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with
equal load conditions. Using the same type of input on each device, the outputs are measured at the differential cross points.
250 ps
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
117 221 fs
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
89 110 fs
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
85 110 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
52 107 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
40 78 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
39 78 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
51 112 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
37 85 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
36 85 fs
t
R
/ t
F
Output Rise/ Fall Time
10% to 90%
outputs loaded with 100
270 400 ps
20% to 80%
outputs loaded with 100
162 260 ps
IDT8P34S1106NLGI Data Sheet 1:6 LVDS Output 1.8V Fanout Buffer
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014 6 ©2014 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA 100 A Signal Generator
as the input source.
Additive Phase Jitter @ 122.88MHz
10kHz to 20MHz – 89fs (typical)
Offset from Carrier Frequency (Hz)
SSB Phase Noise dBc/Hz

8P34S1106NLGI

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IDT
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Clock Drivers & Distribution 1:6 LVDS Output 1.8V Fanout Buffer
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