MC74LVXT8053DTR2

Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 4
1 Publication Order Number:
MC74LVXT8053/D
MC74LVXT8053
Analog Multiplexer /
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT8053 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from V
CC
to GND).
The LVXT8053 is similar in pinout to the high−speed HC4053A,
and the metal−gate MC14053B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means
of an analog switch to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with
TTL−type input thresholds. The input protection circuitry on this
device allows overvoltage tolerance on the input, allowing the device
to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V
CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the higher−voltage power supply.
The MC74LVXT8053 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVXT8053 to be used to interface 5.0 V circuits to
3.0 V circuits.
This device has been designed so that the ON resistance (R
on
) is
more linear over input voltage than R
on
of metal−gate CMOS analog
switches.
Features
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (V
CC
− GND) = 2.0 V to 6.0 V
Digital (Control) Power Supply Range (V
CC
− GND) = 2.0 V to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
Low Noise
In Compliance With the Requirements of JEDEC Standard No. 7A
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
M SUFFIX
CASE 966
SOIC−16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
LVXT8053
AWLYWW
LVXT
8053
ALYW
LVXT8053
ALYW
1
16
1
16
1
16
MC74LVXT8053
http://onsemi.com
2
X0
12
X1
13
A
11
B
10
C
9
ENABLE
6
X SWITCH
Y SWITCH
X
14
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS
PIN 16 = V
CC
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
Y0
2
Y1
1
Y
15
Z0
5
Z1
3
Z
4
Z SWITCH
NOTE: This device allows independent control of each switch. Channel−Select Input A
controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch
Figure 1. LOGIC DIAGRAM
Triple Single−Pole, Double−Position Plus Common Off
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
1516 14 13 12 11 10
21 34567
V
CC
9
8
Y X X1 X0 A B C
Y1 Y0 Z1 Z Z0 Enable NC GND
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
FUNCTION TABLE − MC74LVXT8053
Control Inputs
ON Channels
Enable
Select
CBA
L
L
L
L
L
L
L
L
H
X = Don’t Care
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
X0
X1
X0
X1
NONE
ORDERING INFORMATION
Device Package Shipping
MC74LVXT8053DR2 SOIC−16 2500 Tape & Reel
MC74LVXT8053DR2G SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74LVXT8053DTR2 TSSOP−16* 2500 Tape & Reel
MC74LVXT8053M SOEIAJ−16 50 Units / Rail
MC74LVXT80531MG SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74LVXT8053MEL SOEIAJ−16 2000 Tape & Reel
MC74LVXT8053MELG SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74LVXT8053
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
Positive DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V
V
IS
Analog Input Voltage −0.5 to V
CC
+ 0.5 V
V
in
Digital Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I DC Current, Into or Out of Any Pin −20 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature Range –65 to + 150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Derating SOIC Package: – 7 mW/°C from 65°C to 125°C
TSSOP Package: − 6.1 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
IS
Analog Input Voltage 0.0 V
CC
V
V
in
Digital Input Voltage (Referenced to GND) GND V
CC
V
V
IO
* Static or Dynamic Voltage Across Switch 1.2 V
T
A
Operating Temperature Range, All Package Types –55 + 85 °C
t
r
, t
f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
= 3.3 V ± 0.3 V
V
CC
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
*For voltage drops across switch greater than 1.2 V (switch on), excessive V
CC
current may be
drawn; i.e., the current out of the switch may contain both V
CC
and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS Digital Section (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Condition
V
CC
V
−55 to 25°C 85°C 125°C
Unit
V
IH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
R
on
= Per Spec 3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
R
on
= Per Spec 3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
I
in
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
V
in
= V
CC
or GND, 5.5 ± 0.1 ± 1.0 ± 1.0 A
I
CC
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
V
IS
= V
CC
or GND; V
IO
= 0 V
5.5 4 40 160 A
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND (V
in
or V
out
) V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74LVXT8053DTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC MUX/DEMUX TRIPLE 2X1 16TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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